Add Canaan K230 SoC with sysreset support, running without cache
enabled.
Signed-off-by: Junhui Liu <junhui....@pigmoral.tech>
---
arch/riscv/Kconfig | 5 +++++
arch/riscv/cpu/k230/Kconfig | 14 ++++++++++++++
arch/riscv/cpu/k230/Makefile | 6 ++++++
arch/riscv/cpu/k230/cpu.c | 9 +++++++++
arch/riscv/cpu/k230/dram.c | 21 +++++++++++++++++++++
5 files changed, 55 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index
a160d24fb033eafeee70971a1bff12b545d23a2e..faf70cb5d4c7987b40f46234a26276bc10d270bb
100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,9 @@ config TARGET_ANDES_AE350
config TARGET_BANANAPI_F3
bool "Support BananaPi F3 Board"
+config TARGET_K230_CANMV
+ bool "Support K230 CanMV Board"
+
config TARGET_LICHEERV_NANO
bool "Support LicheeRV Nano Board"
@@ -91,6 +94,7 @@ config SPL_ZERO_MEM_BEFORE_USE
# board-specific options below
source "board/andestech/ae350/Kconfig"
source "board/aspeed/ibex_ast2700/Kconfig"
+source "board/canaan/k230_canmv/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
@@ -113,6 +117,7 @@ source "arch/riscv/cpu/ast2700/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
source "arch/riscv/cpu/jh7110/Kconfig"
source "arch/riscv/cpu/k1/Kconfig"
+source "arch/riscv/cpu/k230/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/k230/Kconfig b/arch/riscv/cpu/k230/Kconfig
new file mode 100644
index
0000000000000000000000000000000000000000..d76ad92a04908f1be3002ce95f13637ce9e96722
--- /dev/null
+++ b/arch/riscv/cpu/k230/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2025, Junhui Liu <junhui....@pigmoral.tech>
+
+config CANAAN_K230
+ bool
+ select ARCH_EARLY_INIT_R
+ select BINMAN
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply CMD_CPU
+ imply SYSRESET
+ imply SYSRESET_SYSCON
diff --git a/arch/riscv/cpu/k230/Makefile b/arch/riscv/cpu/k230/Makefile
new file mode 100644
index
0000000000000000000000000000000000000000..6e321cf3ed19525656efa2c58270e7a9800c9002
--- /dev/null
+++ b/arch/riscv/cpu/k230/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2025, Junhui Liu <junhui....@pigmoral.tech>
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/k230/cpu.c b/arch/riscv/cpu/k230/cpu.c
new file mode 100644
index
0000000000000000000000000000000000000000..417a25f0a8ba33e3ed288860a27c64a4a584cc6b
--- /dev/null
+++ b/arch/riscv/cpu/k230/cpu.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025, Junhui Liu <junhui....@pigmoral.tech>
+ */
+
+int cleanup_before_linux(void)
+{
+ return 0;
+}
diff --git a/arch/riscv/cpu/k230/dram.c b/arch/riscv/cpu/k230/dram.c
new file mode 100644
index
0000000000000000000000000000000000000000..b2d3e4fd6a96d7fc6ca8b8507f4eba85f7e9c9b5
--- /dev/null
+++ b/arch/riscv/cpu/k230/dram.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com>
+ */
+
+#include <asm/global_data.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
--
2.47.1
