On Sat, Dec 28, 2024 at 04:29:39AM +0000, Abbarapu, Venkatesh wrote:
> Hi Tom,
>
> > -----Original Message-----
> > From: Tom Rini <tr...@konsulko.com>
> > Sent: Friday, December 27, 2024 11:53 PM
> > To: Abbarapu, Venkatesh <venkatesh.abbar...@amd.com>
> > Cc: u-boot@lists.denx.de; tudor.amba...@linaro.org; j-humphr...@ti.com;
> > ma...@denx.de; Simek, Michal <michal.si...@amd.com>;
> > ja...@amarulasolutions.com; vigne...@ti.com; u-kum...@ti.com;
> > sean...@gmail.com; caleb.conno...@linaro.org; s...@chromium.org;
> > william.zh...@broadcom.com; stefa...@posteo.net; quentin.sch...@cherry.de;
> > takahiro.kuw...@infineon.com; p-mant...@ti.com; git (AMD-Xilinx)
> > <g...@amd.com>
> > Subject: Re: [PATCH v5] mtd: spi-nor: Fix the spi_nor_read() when config
> > SPI_STACKED_PARALLEL is enabled
> >
> > On Fri, Dec 27, 2024 at 10:19:34AM +0530, Venkatesh Yadav Abbarapu wrote:
> >
> > > Update the spi_nor_read() function based on the config SPI_FLASH_BAR
> > > and update the length and bank calculation by spliting the memory of
> > > 16MB size banks only when the address width is 3byte.
> > > Fix the read issue for 4byte address width by passing the entire
> > > length to the read function. Also update the size when the
> > > configuration is stacked.
> > >
> > > Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories
> > > support")
> > > Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com>
> >
> > I don't think you've run this through CI?
> > https://source.denx.de/u-boot/u-boot/-/jobs/984698#L289 and similar on all
> > sandbox
> > targets, and Azure shows it too.
> >
>
> Ok...Could you please run the CI on the "v3 patch" once, as this patch is
> entirely separated the parallel code with the default one.
>
> [PATCH v3] mtd: spi-nor: Fix the spi_nor_read() when config
> SPI_STACKED_PARALLEL is enabledYes, v3 passes CI. Does the help with what you need to do for v6 then? -- Tom
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