On 10/31/24 7:56 AM, Tudor Ambarus wrote:
Hi, Michal,
Hi,
On 10/30/24 3:20 PM, Michal Simek wrote:
Jagan is aware that we are using this configuration for quite a long
time and we are still here and not leaving.
Okay, great. Would be good if you/your team can allocate time and
review/test patches that are improving/fixing the stacked/parallel bits.
Help in reviewing other SPI NOR bits is appreciated as well.
It seems that over the years , there are no other users of this
"stacked/parallel" functionality but Xilinx ?
Also, how does that work if one SPI NOR suffers a command failure while
the other SPI NOR succeeds to execute the command ? Is that somehow
handled, or is there an assumption that both SPI NORs behave the same
way and can never fail independently (which seems like a dangerous
assumption to make) ?
