From: Ye Li <ye...@nxp.com> To support OSCCA enabled part which has disabled FSB access from SOC, change directly read from FSB to use fuse_read API.
Reviewed-by: Peng Fan <peng....@nxp.com> Signed-off-by: Ye Li <ye...@nxp.com> Signed-off-by: Peng Fan <peng....@nxp.com> --- arch/arm/mach-imx/imx9/soc.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 7df3c686350..42c6deedbf2 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -96,10 +96,14 @@ int mmc_get_env_dev(void) */ u32 get_cpu_speed_grade_hz(void) { + int ret; u32 speed, max_speed; u32 val; - fuse_read(2, 3, &val); + ret = fuse_read(2, 3, &val); + if (ret) + val = 0; /* If read fuse failed, return as blank fuse */ + val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF; speed = MHZ(2300) - val * MHZ(100); @@ -122,9 +126,13 @@ u32 get_cpu_speed_grade_hz(void) */ u32 get_cpu_temp_grade(int *minc, int *maxc) { + int ret; u32 val; - fuse_read(2, 3, &val); + ret = fuse_read(2, 3, &val); + if (ret) + val = 0; /* If read fuse failed, return as blank fuse */ + val = FIELD_GET(MARKETING_GRADING_MASK, val); if (minc && maxc) { @@ -160,9 +168,17 @@ static void set_cpu_info(struct ele_get_info_data *info) static u32 get_cpu_variant_type(u32 type) { - /* word 19 */ - u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); - u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2)); + u32 val, val2; + int ret; + + ret = fuse_read(2, 3, &val); + if (ret) + val = 0; /* If read fuse failed, return as blank fuse */ + + ret = fuse_read(2, 4, &val2); + if (ret) + val2 = 0; /* If read fuse failed, return as blank fuse */ + bool npu_disable = !!(val & BIT(13)); bool core1_disable = !!(val & BIT(15)); u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24); -- 2.35.3