TI's J7200 SoC has a single instance of PCIe Controller namely PCIe1 which is a Cadence PCIe Controller. To support PCI functionality with the PCIe1 instance of PCIe, enable the corresponding configs.
Signed-off-by: Siddharth Vadapalli <s-vadapa...@ti.com> --- configs/j7200_evm_a72_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index fcfa926599..5a8cc0e6a7 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set +CONFIG_PCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 @@ -72,6 +73,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y @@ -154,6 +156,8 @@ CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83869=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PCI_CONFIG_HOST_BRIDGE=y +CONFIG_PCIE_CDNS_TI=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_TORRENT=y -- 2.40.1
