On 8/14/24 12:17 AM, Chintan Vankar wrote:
On 13/08/24 23:57, Andrew Davis wrote:
On 8/12/24 6:48 AM, Chintan Vankar wrote:
From: Kishon Vijay Abraham I <kis...@ti.com>
In order to support Ethernet boot on AM62x, probe AM65 CPSW NUSS
driver in board_init_f().
Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapa...@ti.com>
Signed-off-by: Chintan Vankar <c-van...@ti.com>
---
Link to v4:
https://lore.kernel.org/r/20240705045030.1141934-7-c-van...@ti.com/
Changes from v3 to v4:
- No changes.
arch/arm/mach-k3/am62x/am625_init.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-k3/am62x/am625_init.c
b/arch/arm/mach-k3/am62x/am625_init.c
index 72a752d38e..0182c153a6 100644
--- a/arch/arm/mach-k3/am62x/am625_init.c
+++ b/arch/arm/mach-k3/am62x/am625_init.c
@@ -280,6 +280,16 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
}
+
+ if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
+ spl_boot_device() == BOOT_DEVICE_ETHERNET) {
+ struct udevice *cpswdev;
+
+ if (uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(am65_cpsw_nuss),
+ &cpswdev))
+ printf("Failed to probe am65_cpsw_nuss driver\n");
+ }
+
spl_enable_cache();
Any reason you added this before enabling caches?
Andrew
There is no specific reason for it, I can probe CPSW driver after
enabling cache also.
Let's do that then. We enable caches right after enabling DRAM to keep
the amount of non-cached DDR accesses low.
Andrew
fixup_a53_cpu_freq_by_speed_grade();
