After the commit aca95282c1b7 ("Makefile: Use the fdtgrep -u flag")
bootph props is propagating to parent nodes.
Update bootph props to ensure eMMC, SD-card and SPI flash is available
in SPL and U-Boot proper pre-reloc phase also remove unneeded bootph
props that automatically is propagated to parent nodes.
Also adjust pinctrl nodes to only be included in boot phases where they
are needed and add any missing pinctrl node needed in SPL.
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
v2: Add bootph-some-ram props and follow kernel sort order
Following bootph props have been applied:
CRU, GRF and UART nodes:
- bootph-all - needed at all or most stages
SD-card regulator related nodes:
- bootph-pre-ram (SPL) - regulator pinctrl may be needed to read FIT
from SD-card on some boards
eMMC/SD-card/SPI flash related nodes:
- bootph-pre-ram (SPL)
- bootph-some-ram (U-Boot proper pre-reloc)
---
arch/arm/dts/rk3566-pinetab2-u-boot.dtsi | 25 +++++++----
arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 8 ++--
arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 4 +-
arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 7 ++-
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 5 +--
arch/arm/dts/rk356x-u-boot.dtsi | 51 ++++++++++++++--------
configs/evb-rk3568_defconfig | 3 +-
7 files changed, 61 insertions(+), 42 deletions(-)
diff --git a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
index 4aa6ab1c848c..eb18008f2fe3 100644
--- a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
@@ -3,20 +3,31 @@
#include "rk356x-u-boot.dtsi"
&fspi_dual_io_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&gpio0 {
- bootph-all;
+ bootph-pre-ram;
};
&i2c0 {
bootph-pre-ram;
};
+&i2c0_xfer {
+ bootph-pre-ram;
+};
+
+&i2s1m0_mclk {
+ bootph-pre-ram;
+};
+
+&pmic_int_l {
+ bootph-pre-ram;
+};
+
&rk817 {
- bootph-pre-ram;
-
regulators {
bootph-pre-ram;
};
@@ -27,15 +38,13 @@
};
&sdmmc_pwren_l {
- bootph-all;
+ bootph-pre-ram;
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
index 930d660868bb..0e25b7e108fc 100644
--- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
@@ -3,7 +3,7 @@
#include "rk356x-u-boot.dtsi"
&gpio0 {
- bootph-all;
+ bootph-pre-ram;
};
&sdhci {
@@ -13,11 +13,9 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
@@ -34,5 +32,5 @@
};
&vcc_sd_h {
- bootph-all;
+ bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
index c235b4357f7d..f2c9d8e167d5 100644
--- a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
@@ -9,11 +9,9 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
index 1fc71faa9e07..d8a6dd87510f 100644
--- a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
@@ -3,7 +3,8 @@
#include "rk356x-u-boot.dtsi"
&fspi_dual_io_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdhci {
@@ -15,10 +16,8 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
-
flash@0 {
bootph-pre-ram;
+ bootph-some-ram;
};
};
diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index 5b823fcca5fb..9d18f5d0b364 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -26,16 +26,15 @@
};
&sfc {
- bootph-pre-ram;
- u-boot,spl-sfc-no-dma;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
- bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
+ bootph-pre-ram;
+ bootph-some-ram;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index 1ecf719202e9..ffac4a9def51 100644
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -43,43 +43,46 @@
};
&emmc_bus8 {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_clk {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_cmd {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_datastrobe {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&emmc_rstnout {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&fspi_pins {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&grf {
bootph-all;
};
-&i2c0_xfer {
- bootph-all;
-};
-
&pcfg_pull_none {
bootph-all;
};
&pcfg_pull_none_smt {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&pcfg_pull_up {
@@ -87,7 +90,8 @@
};
&pcfg_pull_up_drv_level_2 {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl {
@@ -104,35 +108,46 @@
&sdhci {
bootph-pre-ram;
+ bootph-some-ram;
max-frequency = <200000000>;
};
&sdmmc0 {
bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_bus4 {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_clk {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_cmd {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_det {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
};
&sdmmc0_pwren {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sfc {
+ u-boot,spl-sfc-no-dma;
};
&uart2 {
- bootph-pre-ram;
+ bootph-all;
clock-frequency = <24000000>;
};
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 6e8061f5f487..37b4c5955994 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -32,7 +32,7 @@ CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
@@ -49,6 +49,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
--
2.43.2
