From: Ashok Reddy Soma <ashok.reddy.s...@xilinx.com> This patch cleans up the cadence qspi registers in the init. The register contents may be invalid if this controller is used in previous boot and comes to uboot after a softreset (no power on reset). This may cause issues in uboot.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.s...@xilinx.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhum...@amd.com> --- drivers/spi/cadence_qspi_apb.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7576dacfb0..35a21a2727 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -340,12 +340,34 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv) /* Configure the remap address register, no remap */ writel(0, priv->regbase + CQSPI_REG_REMAP); + /* Clear instruction read config register */ + writel(0, priv->regbase + CQSPI_REG_RD_INSTR); + + /* Reset the Delay lines */ + writel(CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK, + priv->regbase + CQSPI_REG_PHY_CONFIG); + + reg = readl(priv->regbase + CQSPI_REG_RD_DATA_CAPTURE); + reg &= ~CQSPI_REG_READCAPTURE_DQS_ENABLE; + reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK + << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); + writel(reg, priv->regbase + CQSPI_REG_RD_DATA_CAPTURE); + /* Indirect mode configurations */ writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION); /* Disable all interrupts */ writel(0, priv->regbase + CQSPI_REG_IRQMASK); + reg = readl(priv->regbase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_DTR_PROT_EN_MASK; + reg &= ~CQSPI_REG_CONFIG_PHY_ENABLE_MASK; + reg &= ~CQSPI_REG_CONFIG_DIRECT; + reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK + << CQSPI_REG_CONFIG_CHIPSELECT_LSB); + + writel(reg, priv->regbase + CQSPI_REG_CONFIG); + cadence_qspi_apb_controller_enable(priv->regbase); } -- 2.27.0