From: Ashok Reddy Soma <ashok.reddy.s...@amd.com>
Incase of non-aligned length of flash data, ahbbase address is written
directly with byte count. This is causing AHB bus error's sometimes and
resulting in kernel crash while booting linux. To avoid this write 4 byte
aligned byte count to ahbbase address.
Also use a temporary variable with 0xffffffff data and overwrite this
temp with unaligned bytes data before writing to ahbbase.
The value 0xffffffff is chosen as this is flash memory, worst case we
will write 0xff to any location which doesn't effect any bits.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.s...@amd.com>
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhum...@amd.com>
---
drivers/spi/cadence_qspi_apb.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 4404b0ba07..7576dacfb0 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -891,10 +891,12 @@ cadence_qspi_apb_indirect_write_execute(struct
cadence_spi_priv *priv,
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
writesl(priv->ahbbase, bb_txbuf, write_bytes >> 2);
- if (write_bytes % 4)
- writesb(priv->ahbbase,
- bb_txbuf + rounddown(write_bytes, 4),
- write_bytes % 4);
+ if (write_bytes % 4) {
+ unsigned int temp = 0xffffffff;
+
+ memcpy(&temp, bb_txbuf + rounddown(write_bytes, 4),
write_bytes % 4);
+ writel(temp, priv->ahbbase);
+ }
ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_SDRAMLEVEL,
CQSPI_REG_SDRAMLEVEL_WR_MASK <<
--
2.27.0
