On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote: > From: Haiying Wang <haiying.w...@freescale.com> > > P1021 has some QE pins which need to be set in pmuxcr register before > using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and > UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to > be released after MII access because QE12 pin is muxed with LBCTL signal. > > Also added relevant QE support defines unique to P1021. > > The P1021 QE is shared on P1012, P1016, and P1025. > > Signed-off-by: Haiying Wang <haiying.w...@freescale.com> > Signed-off-by: Kumar Gala <ga...@kernel.crashing.org> > --- > arch/powerpc/cpu/mpc85xx/speed.c | 8 +++++- > arch/powerpc/include/asm/config_mpc85xx.h | 12 +++++++++ > arch/powerpc/include/asm/immap_85xx.h | 38 ++++++++++++++++++++++------- > drivers/qe/uec.c | 37 +++++++++++++++++++++++++++- > 4 files changed, 84 insertions(+), 11 deletions(-)
applied to 85xx - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
