From: bhaskar upadhaya <bhaskar.upadh...@freescale.com>
Fix up the device tree property associated with the IEEE 1588 timer
source frequency. Currently we only support the IEEE 1588 timer source
being the internal eTSEC system clock (for those SoCs with IEEE 1588
support). The eTSEC clock is ccb_clk/2.
Signed-off-by: Bhaskar Upadhaya <bhaskar.upadh...@freescale.com>
Signed-off-by: Kumar Gala <ga...@kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/fdt.c | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 6ed0284..642f6c5 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -486,4 +486,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SYS_SRIO
ft_srio_setup(blob);
#endif
+
+ /*
+ * system-clock = CCB clock/2
+ * Here gd->bus_clk = CCB clock
+ * We are using the system clock as 1588 Timer reference
+ * clock source select
+ */
+ do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
+ "timer-frequency", gd->bus_clk/2, 1);
}
--
1.7.2.3
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