In the current implementation, the test for data ranging from 0 to 8 bytes
is encountering failures. This has been confirmed through testing with both
ISSI (IS25WX256) and Micron (MT35XU02G) Flash in SDR mode exclusively.
Upon analysis, it was observed that utilizing the "SPI_NOR_OCTAL_READ"
flag and attempting to read less than 8 bytes in STIG mode results in a
failure to read, leading to a failure in the compare test.
Upon reviewing the Micron OSPI flash data sheet, it was noted that for
protocol 1-1-8, 8 dummy clock cycles are required. While the current
implementation achieves this, it still results in a compare test failure.
Therefore, the code has been revised to include DMA read for operations
involving less than 8 bytes as well.
Fixes: 53f4ef0 ("spi: cadence_qspi: use STIG mode for small reads")
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhum...@amd.com>
---
drivers/spi/cadence_qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index dfc74c882d..a6477dbfcf 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -313,7 +313,7 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
* which is unsupported on some flash devices during register
* reads, prefer STIG mode for such small reads.
*/
- if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
+ if (!op->addr.nbytes)
mode = CQSPI_STIG_READ;
else
mode = CQSPI_READ;
--
2.27.0
