T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.
Tested-by: Agneli <po...@protonmail.ch> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <longnose...@gmail.com> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <hed...@yahoo.com> # ASUS Grouper E1565
Tested-by: Ion Agorria <i...@agorria.com> # HTC One X
Tested-by: Svyatoslav Ryhel <clamo...@gmail.com> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <clamo...@gmail.com>
---
drivers/video/tegra20/tegra-dc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 0e94e665ef..56a23b3c97 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -304,6 +304,12 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
if (priv->dc_clk[1] == CLOCK_ID_DISPLAY)
rate /= 2;
+#ifndef CONFIG_TEGRA20
+ /* PLLD2 obeys same rules as PLLD but it is present only on T30+ */
+ if (priv->dc_clk[1] == CLOCK_ID_DISPLAY2)
+ rate /= 2;
+#endif
+
/*
* HOST1X is init by default at 150MHz with PLLC as parent
*/
--
2.40.1
