Hi Michael,
Curiously, have any idea how to test cache stuff?
2011/3/18 Michael Spang <msp...@csclub.uwaterloo.ca>:
> If U-Boot is loaded from RAM and the OS is loaded into an overlapping
> region, the instruction cache is not coherent when that OS is started.
> We must therefore invalidate the instruction cache in addition to
> cleaning the data cache.
>
> Signed-off-by: Michael Spang <msp...@csclub.uwaterloo.ca>
> ---
> arch/arm/lib/cache.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
> index 30686fe..047786a 100644
> --- a/arch/arm/lib/cache.c
> +++ b/arch/arm/lib/cache.c
> @@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long
> dummy2)
> asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
> /* disable write buffer as well (page 2-22) */
> asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
> + /* invalidate icache for coherence with cleaned dcache */
> + asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
> #endif
> #ifdef CONFIG_OMAP34XX
> void v7_flush_cache_all(void);
> --
> 1.7.2.3
>
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>
--
cheers,
jay
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