On 7/21/23 07:45, Andre Przywara wrote:
For the first time since at least the Allwinner A10 SoCs, the D1 (and related cores) use a new pincontroller MMIO register layout, so we cannot use our hardcoded, fixed offsets anymore. Ideally this would all be handled by devicetree and DM drivers, but for the DT-less SPL we still need the legacy interfaces. Add a new Kconfig symbol to differenciate between the two generations of pincontrollers, and just use that to just switch some basic symbols. The rest is already abstracted enough, so works out of the box. Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Reviewed-by: Sam Edwards <cfswo...@gmail.com> Tested-by: Sam Edwards <cfswo...@gmail.com> Thanks, Sam
