This version has been tested on an armputer-vmax board, which is similar to the at91sam9263ek but not on the at91sam9263ek board itself. A new configuration "armputer-vmax_config" has been added. This configuration has been tested on the hardware and is known to work. Further hardware tests for individual options are needed. The LCD screen was not tested.
--- Makefile | 1 - arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c | 3 +- arch/arm/cpu/arm926ejs/at91/clock.c | 2 +- arch/arm/cpu/arm926ejs/at91/cpu.c | 2 +- arch/arm/cpu/arm926ejs/at91/reset.c | 2 +- arch/arm/cpu/arm926ejs/at91/timer.c | 10 +- arch/arm/include/asm/arch-at91/at91_pio.h | 6 +- arch/arm/include/asm/arch-at91/at91sam9263.h | 170 +++++++++++---------- arch/arm/lib/board.c | 1 + board/atmel/at91sam9263ek/at91sam9263ek.c | 13 +- board/atmel/at91sam9263ek/led.c | 19 +-- boards.cfg | 2 + drivers/gpio/at91_gpio.c | 44 +++--- drivers/serial/atmel_usart.c | 12 +- drivers/spi/atmel_dataflash_spi.c | 78 ++++------ drivers/usb/host/ohci-at91.c | 6 +- include/configs/at91sam9263ek.h | 122 ++++++++------- 17 files changed, 251 insertions(+), 242 deletions(-) diff --git a/Makefile b/Makefile index 6133160..0c653fa 100644 --- a/Makefile +++ b/Makefile @@ -827,7 +827,6 @@ at91sam9263ek_norflash_config \ at91sam9263ek_norflash_boot_config \ at91sam9263ek_nandflash_config \ at91sam9263ek_dataflash_config \ -at91sam9263ek_dataflash_cs0_config \ at91sam9263ek_config : unconfig @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c index deda3e5..d58f8e4 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -26,9 +26,10 @@ * MA 02111-1307 USA */ +#include <config.h> #include <common.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> +#include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pio.h> diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 608af2c..37b0335 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -145,7 +145,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg) int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; #ifndef CONFIG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c index c47fb31..df77097 100644 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ b/arch/arm/cpu/arm926ejs/at91/cpu.c @@ -43,7 +43,7 @@ int arch_cpu_init(void) void arch_preboot_os(void) { ulong cpiv; - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c index 023719a..22a8cb3 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/cpu/arm926ejs/at91/reset.c @@ -30,7 +30,7 @@ /* Reset the cpu by telling the reset controller to do so */ void reset_cpu(ulong ignored) { - at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST /* Processor Reset */ diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index a087687..38be95a 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -70,11 +70,11 @@ static inline unsigned long long usec_to_tick(unsigned long long usec) */ int timer_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; /* Enable PITC Clock */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); + writel(1 << AT91_ID_SYS, &pmc->pcer); /* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); @@ -90,7 +90,7 @@ int timer_init(void) */ unsigned long long get_ticks(void) { - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; ulong now = readl(&pit->piir); @@ -109,7 +109,7 @@ void __udelay(unsigned long usec) start = get_ticks(); /* get current timestamp */ tmo = usec_to_tick(usec); /* convert usecs to ticks */ while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ + ; /* loop till time has passed */ } /* diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 0b5bd69..4e0a5cd 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -81,14 +81,14 @@ typedef union at91_pio { at91_port_t pioa; at91_port_t piob; at91_port_t pioc; - #if (ATMEL_PIO_PORTS > 3) + #if (AT91_PIO_PORTS > 3) at91_port_t piod; #endif - #if (ATMEL_PIO_PORTS > 4) + #if (AT91_PIO_PORTS > 4) at91_port_t pioe; #endif } ; - at91_port_t port[ATMEL_PIO_PORTS]; + at91_port_t port[AT91_PIO_PORTS]; } at91_pio_t; #ifdef CONFIG_AT91_GPIO diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index bfd408b..0aad302 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -20,118 +20,124 @@ /* * defines to be used in other places */ -#define CONFIG_ARM926EJS /* ARM926EJS Core */ +//#define CONFIG_ARM926EJS /* ARM926EJS Core */ #define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* * Peripheral identifiers/interrupts. */ -#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define ATMEL_ID_SYS 1 /* System Peripherals */ -#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ -#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ -#define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ /* Reserved: 5 */ /* Reserved: 6 */ -#define ATMEL_ID_USART0 7 /* USART 0 */ -#define ATMEL_ID_USART1 8 /* USART 1 */ -#define ATMEL_ID_USART2 9 /* USART 2 */ -#define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define ATMEL_ID_CAN 12 /* CAN */ -#define ATMEL_ID_TWI 13 /* Two-Wire Interface */ -#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define ATMEL_ID_AC97C 18 /* AC97 Controller */ -#define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define ATMEL_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9263_ID_US0 7 /* USART 0 */ +#define AT91SAM9263_ID_US1 8 /* USART 1 */ +#define AT91SAM9263_ID_US2 9 /* USART 2 */ +#define AT9SAM92631_ID_MCI0 10 /* Multimedia Card Interface 0 */ +#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ +#define AT91SAM9263_ID_CAN 12 /* CAN */ +#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ +#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ +#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ +#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ +#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ +#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ +#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ /* Reserved: 22 */ -#define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */ -#define ATMEL_ID_UDP 24 /* USB Device Port */ -#define ATMEL_ID_ISI 25 /* Image Sensor Interface */ -#define ATMEL_ID_LCDC 26 /* LCD Controller */ -#define ATMEL_ID_DMA 27 /* DMA Controller */ +#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ +#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ +#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ +#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ +#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ /* Reserved: 28 */ #define ATMEL_ID_UHP 29 /* USB Host port */ -#define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ /* * User Peripherals physical base addresses. */ -#define ATMEL_BASE_UDP 0xfff78000 -#define ATMEL_BASE_TCB0 0xfff7c000 -#define ATMEL_BASE_TC0 0xfff7c000 -#define ATMEL_BASE_TC1 0xfff7c040 -#define ATMEL_BASE_TC2 0xfff7c080 -#define ATMEL_BASE_MCI0 0xfff80000 -#define ATMEL_BASE_MCI1 0xfff84000 -#define ATMEL_BASE_TWI 0xfff88000 -#define ATMEL_BASE_USART0 0xfff8c000 -#define ATMEL_BASE_USART1 0xfff90000 -#define ATMEL_BASE_USART2 0xfff94000 -#define ATMEL_BASE_SSC0 0xfff98000 -#define ATMEL_BASE_SSC1 0xfff9c000 -#define ATMEL_BASE_AC97C 0xfffa0000 -#define ATMEL_BASE_SPI0 0xfffa4000 -#define ATMEL_BASE_SPI1 0xfffa8000 -#define ATMEL_BASE_CAN 0xfffac000 -#define ATMEL_BASE_PWMC 0xfffb8000 -#define ATMEL_BASE_EMAC 0xfffbc000 -#define ATMEL_BASE_ISI 0xfffc4000 -#define ATMEL_BASE_2DGE 0xfffc8000 +/* + * User Peripheral physical base addresses. + */ +#define AT91_UDP_BASE 0xfff78000 +#define AT91_TCB0_BASE 0xfff7c000 +#define AT91_TC0_BASE 0xfff7c000 +#define AT91_TC1_BASE 0xfff7c040 +#define AT91_TC2_BASE 0xfff7c080 +#define AT91_MCI0_BASE 0xfff80000 +#define AT91_MCI1_BASE 0xfff84000 +#define AT91_TWI_BASE 0xfff88000 +#define AT91_USART0_BASE 0xfff8c000 +#define AT91_USART1_BASE 0xfff90000 +#define AT91_USART2_BASE 0xfff94000 +#define AT91_SSC0_BASE 0xfff98000 +#define AT91_SSC1_BASE 0xfff9c000 +#define AT91_AC97C_BASE 0xfffa0000 +#define AT91_SPI0_BASE 0xfffa4000 +#define AT91_SPI1_BASE 0xfffa8000 +#define AT91_CAN_BASE 0xfffac000 +#define AT91_PWMC_BASE 0xfffb8000 +#define AT91_EMAC_BASE 0xfffbc000 +#define AT91_ISI_BASE 0xfffc4000 +#define AT91_2DGE_BASE 0xfffc8000 /* * System Peripherals physical base addresses. */ -#define ATMEL_BASE_ECC0 0xffffe000 -#define ATMEL_BASE_SDRAMC0 0xffffe200 -#define ATMEL_BASE_SMC0 0xffffe400 -#define ATMEL_BASE_ECC1 0xffffe600 -#define ATMEL_BASE_SDRAMC1 0xffffe800 -#define ATMEL_BASE_SMC1 0xffffea00 -#define ATMEL_BASE_MATRIX 0xffffec00 -#define ATMEL_BASE_CCFG 0xffffed10 -#define ATMEL_BASE_DBGU 0xffffee00 -#define ATMEL_BASE_AIC 0xfffff000 -#define ATMEL_BASE_PIOA 0xfffff200 -#define ATMEL_BASE_PIOB 0xfffff400 -#define ATMEL_BASE_PIOC 0xfffff600 -#define ATMEL_BASE_PIOD 0xfffff800 -#define ATMEL_BASE_PIOE 0xfffffa00 -#define ATMEL_BASE_PMC 0xfffffc00 -#define ATMEL_BASE_RSTC 0xfffffd00 -#define ATMEL_BASE_SHDWC 0xfffffd10 -#define ATMEL_BASE_RTT0 0xfffffd20 -#define ATMEL_BASE_PIT 0xfffffd30 -#define ATMEL_BASE_WDT 0xfffffd40 -#define ATMEL_BASE_RTT1 0xfffffd50 -#define ATMEL_BASE_GPBR 0xfffffd60 +#define AT91_ECC0_BASE 0xffffe000 +#define AT91_SDRAMC0_BASE 0xffffe200 +#define AT91_SMC0_BASE 0xffffe400 +#define AT91_ECC1_BASE 0xffffe600 +#define AT91_SDRA_BASEMC1 0xffffe800 +#define AT91_SMC1_BASE 0xffffea00 +#define AT91_MATR_BASEIX 0xffffec00 +#define AT91_CCFG_BASE 0xffffed10 +#define AT91_DBGU_BASE 0xffffee00 +#define AT91_AIC_BASE 0xfffff000 +#define AT91_PIOA_BASE 0xfffff200 +#define AT91_PIOB_BASE 0xfffff400 +#define AT91_PIOC_BASE 0xfffff600 +#define AT91_PIOD_BASE 0xfffff800 +#define AT91_PIOE_BASE 0xfffffa00 +#define AT91_PMC_BASE 0xfffffc00 +#define AT91_RSTC_BASE 0xfffffd00 +#define AT91_SHDW_BASEC 0xfffffd10 +#define AT91_RTT0_BASE 0xfffffd20 +#define AT91_PIT_BASE 0xfffffd30 +#define AT91_WDT_BASE 0xfffffd40 +#define AT91_RTT1_BASE 0xfffffd50 +#define AT91_GPBR_BASE 0xfffffd60 /* * Internal Memory. */ -#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */ +#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ +#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ -#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */ +#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ -#define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */ +#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ +#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ -#define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */ -#define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */ -#define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */ +#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ +#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ +#define AT91_BASE_UHP 0x00a00000 /* USB Host controller */ /* * Other misc defines */ -#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ - +#define AT91_PIO_PORTS 5 /* this SoCs has 5 PIO */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* * Cpu Name */ -#define ATMEL_CPU_NAME "AT91SAM9263" - +#define ATMEL_CPU_NAME "AT91SAM9263" +#define AT91_USART_ID ATMEL_ID_SYS #endif diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index c620d2c..ea81378 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -232,6 +232,7 @@ void __dram_init_banksize(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; + } void dram_init_banksize(void) __attribute__((weak, alias("__dram_init_banksize"))); diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 91efc07..7216022 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -32,7 +32,7 @@ #include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> +#include <asm/io.h> #include <asm/arch/hardware.h> #include <lcd.h> #include <atmel_lcdc.h> @@ -99,7 +99,7 @@ static void at91sam9263ek_macb_hw_init(void) { unsigned long erstl; at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; /* Enable clock */ writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); @@ -225,8 +225,11 @@ void lcd_show_board_info(void) for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; + +#ifdef CONFIG_CMD_NAND for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += nand_info[i].size; +#endif #ifndef CONFIG_SYS_NO_FLASH flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) @@ -255,6 +258,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; at91_serial_hw_init(); + debug ("Ready for debugging messages\n"); #ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); #endif @@ -276,8 +280,9 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; // U.R is this the way to do it? return 0; } diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c index fa1f05b..b3adc51 100644 --- a/board/atmel/at91sam9263ek/led.c +++ b/board/atmel/at91sam9263ek/led.c @@ -23,25 +23,22 @@ */ #include <common.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/arch/at91_pmc.h> void coloured_LED_init(void) { /* Enable clock */ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE, + writel(1 << AT91_ID_PIOB | 1 << AT91_ID_PIOCDE, &pmc->pcer); - at91_set_pio_output(CONFIG_RED_LED, 1); - at91_set_pio_output(CONFIG_GREEN_LED, 1); - at91_set_pio_output(CONFIG_YELLOW_LED, 1); + // at91_set_pio_output(CONFIG_RED_LED, 1); + at91_set_pio_output(CONFIG_GREEN_LED, 0); + at91_set_pio_output(CONFIG_YELLOW_LED, 0); - at91_set_pio_value(CONFIG_RED_LED, 0); - at91_set_pio_value(CONFIG_GREEN_LED, 1); - at91_set_pio_value(CONFIG_YELLOW_LED, 1); + // at91_set_pio_value(CONFIG_RED_LED, 0); + at91_set_pio_value(CONFIG_GREEN_LED, 0); + at91_set_pio_value(CONFIG_YELLOW_LED, 0); } diff --git a/boards.cfg b/boards.cfg index 45c3102..a9a8751 100644 --- a/boards.cfg +++ b/boards.cfg @@ -106,6 +106,8 @@ magnesium arm arm926ejs imx27lite logicpd omap5912osk arm arm926ejs - ti omap edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon +at91sam9263ek_dataflash_cs0 arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH_CS0 +armputer-vmax arm arm926ejs armputer-vmax atmel at91 armputer-vmax:AT91SAM9263,SYS_USE_DATAFLASH_CS0 ca9x4_ct_vxp arm armv7 vexpress armltd efikamx arm armv7 efikamx - mx5 mx51evk arm armv7 mx51evk freescale mx5 diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index be2a026..4520ff2 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -29,7 +29,7 @@ * * As the code is right now, it expects all PIO ports A,B,C,... * to be evenly spaced in the memory map: - * ATMEL_BASE_PIOA + port * sizeof at91pio_t + * AT91_BASE_PIOA + port * sizeof at91pio_t * This might not necessaryly be true in future Atmel SoCs. * This code should be fixed to use a pointer array to the ports. */ @@ -43,10 +43,10 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; if (use_pullup) writel(1 << pin, &pio->port[port].puer); @@ -62,10 +62,10 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) */ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -79,10 +79,10 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -97,10 +97,10 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -116,10 +116,10 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -135,10 +135,10 @@ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) */ int at91_set_pio_output(unsigned port, u32 pin, int value) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); writel(mask, &pio->port[port].pudr); @@ -157,10 +157,10 @@ int at91_set_pio_output(unsigned port, u32 pin, int value) */ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; if (is_on) writel(mask, &pio->port[port].ifer); @@ -176,10 +176,10 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) */ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; if (is_on) writel(mask, &pio->port[port].mder); @@ -194,10 +194,10 @@ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) */ int at91_set_pio_value(unsigned port, unsigned pin, int value) { - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; if (value) writel(mask, &pio->port[port].sodr); @@ -212,11 +212,11 @@ int at91_set_pio_value(unsigned port, unsigned pin, int value) */ int at91_get_pio_value(unsigned port, unsigned pin) { - u32 pdsr = 0; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 pdsr = 0; + at91_pio_t *pio = (at91_pio_t *) AT91_PIOA_BASE; u32 mask; - if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if ((port < AT91_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; pdsr = readl(&pio->port[port].pdsr) & mask; } diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index e326b2b..5ea2b23 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; void serial_setbrg(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t*)AT91_DBGU_BASE; unsigned long divisor; unsigned long usart_hz; @@ -40,14 +40,14 @@ void serial_setbrg(void) * Baud Rate = -------------- * 16 * CD */ - usart_hz = get_usart_clk_rate(CONFIG_USART_ID); + usart_hz = get_usart_clk_rate(AT91_USART_ID); divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; writel(USART3_BF(CD, divisor), &usart->brgr); } int serial_init(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t*)AT91_DBGU_BASE; writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); @@ -66,7 +66,7 @@ int serial_init(void) void serial_putc(char c) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t*)AT91_DBGU_BASE; if (c == '\n') serial_putc('\r'); @@ -83,7 +83,7 @@ void serial_puts(const char *s) int serial_getc(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t*)AT91_DBGU_BASE; while (!(readl(&usart->csr) & USART3_BIT(RXRDY))) WATCHDOG_RESET(); @@ -92,6 +92,6 @@ int serial_getc(void) int serial_tstc(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t*)AT91_DBGU_BASE; return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0; } diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 6e632cc..3575c4d 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -25,7 +25,6 @@ # warning Please update to use C structur SoC access ! #endif #include <common.h> -#include <spi.h> #include <malloc.h> #include <asm/io.h> @@ -33,8 +32,6 @@ #include <asm/arch/clk.h> #include <asm/arch/hardware.h> -#include "atmel_spi.h" - #include <asm/arch/gpio.h> #include <asm/arch/at91_pio.h> #include <asm/arch/at91_spi.h> @@ -49,18 +46,18 @@ void AT91F_SpiInit(void) { /* Reset the SPI */ - writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR); + writel(AT91_SPI_SWRST, AT91_SPI0_BASE + AT91_SPI_CR); /* Configure SPI in Master Mode with No CS selected !!! */ writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS, - ATMEL_BASE_SPI0 + AT91_SPI_MR); + AT91_SPI0_BASE + AT91_SPI_MR); /* Configure CS0 */ writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - ATMEL_BASE_SPI0 + AT91_SPI_CSR(0)); + AT91_SPI0_BASE + AT91_SPI_CSR(0)); #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 /* Configure CS1 */ @@ -68,7 +65,7 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - ATMEL_BASE_SPI0 + AT91_SPI_CSR(1)); + AT91_SPI0_BASE + AT91_SPI_CSR(1)); #endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2 /* Configure CS2 */ @@ -76,7 +73,7 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - ATMEL_BASE_SPI0 + AT91_SPI_CSR(2)); + AT91_SPI0_BASE + AT91_SPI_CSR(2)); #endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 /* Configure CS3 */ @@ -84,22 +81,21 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - ATMEL_BASE_SPI0 + AT91_SPI_CSR(3)); + AT91_SPI0_BASE + AT91_SPI_CSR(3)); #endif /* SPI_Enable */ - writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); + writel(AT91_SPI_SPIEN,AT91_SPI0_BASE + AT91_SPI_CR); - while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS)) - ; + while (!(readl(AT91_SPI0_BASE + AT91_SPI_SR) & AT91_SPI_SPIENS)); /* * Add tempo to get SPI in a safe state. * Should not be needed for new silicon (Rev B) */ udelay(500000); - readl(ATMEL_BASE_SPI0 + AT91_SPI_SR); - readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR); + readl(AT91_SPI0_BASE + AT91_SPI_SR); + readl(AT91_SPI0_BASE + AT91_SPI_RDR); } @@ -109,33 +105,33 @@ void AT91F_SpiEnable(int cs) switch (cs) { case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); + mode = readl(AT91_SPI0_BASE + AT91_SPI_MR); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + AT91_SPI0_BASE + AT91_SPI_MR); break; case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); + mode = readl(AT91_SPI0_BASE + AT91_SPI_MR); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + AT91_SPI0_BASE + AT91_SPI_MR); break; case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */ - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); + mode = readl(AT91_SPI0_BASE + AT91_SPI_MR); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + AT91_SPI0_BASE + AT91_SPI_MR); break; case 3: - mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); + mode = readl(AT91_SPI0_BASE + AT91_SPI_MR); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - ATMEL_BASE_SPI0 + AT91_SPI_MR); + AT91_SPI0_BASE + AT91_SPI_MR); break; } /* SPI_Enable */ - writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); + writel(AT91_SPI_SPIEN,AT91_SPI0_BASE + AT91_SPI_CR); } unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); @@ -147,44 +143,34 @@ unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) pDesc->state = BUSY; - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, - ATMEL_BASE_SPI0 + AT91_SPI_PTCR); + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,AT91_SPI0_BASE + AT91_SPI_PTCR); /* Initialize the Transmit and Receive Pointer */ - writel((unsigned int)pDesc->rx_cmd_pt, - ATMEL_BASE_SPI0 + AT91_SPI_RPR); - writel((unsigned int)pDesc->tx_cmd_pt, - ATMEL_BASE_SPI0 + AT91_SPI_TPR); + writel((unsigned int)pDesc->rx_cmd_pt,AT91_SPI0_BASE + AT91_SPI_RPR); + writel((unsigned int)pDesc->tx_cmd_pt,AT91_SPI0_BASE + AT91_SPI_TPR); /* Intialize the Transmit and Receive Counters */ - writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR); - writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR); + writel(pDesc->rx_cmd_size,AT91_SPI0_BASE + AT91_SPI_RCR); + writel(pDesc->tx_cmd_size,AT91_SPI0_BASE + AT91_SPI_TCR); if (pDesc->tx_data_size != 0) { /* Initialize the Next Transmit and Next Receive Pointer */ - writel((unsigned int)pDesc->rx_data_pt, - ATMEL_BASE_SPI0 + AT91_SPI_RNPR); - writel((unsigned int)pDesc->tx_data_pt, - ATMEL_BASE_SPI0 + AT91_SPI_TNPR); + writel((unsigned int)pDesc->rx_data_pt,AT91_SPI0_BASE + AT91_SPI_RNPR); + writel((unsigned int)pDesc->tx_data_pt,AT91_SPI0_BASE + AT91_SPI_TNPR); /* Intialize the Next Transmit and Next Receive Counters */ - writel(pDesc->rx_data_size, - ATMEL_BASE_SPI0 + AT91_SPI_RNCR); - writel(pDesc->tx_data_size, - ATMEL_BASE_SPI0 + AT91_SPI_TNCR); + writel(pDesc->rx_data_size,AT91_SPI0_BASE + AT91_SPI_RNCR); + writel(pDesc->tx_data_size,AT91_SPI0_BASE + AT91_SPI_TNCR); } /* arm simple, non interrupt dependent timer */ timebase = get_timer(0); timeout = 0; - writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, - ATMEL_BASE_SPI0 + AT91_SPI_PTCR); - while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) && - ((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT)) - ; - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, - ATMEL_BASE_SPI0 + AT91_SPI_PTCR); + writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN,AT91_SPI0_BASE + AT91_SPI_PTCR); + while (!(readl(AT91_SPI0_BASE + AT91_SPI_SR) & AT91_SPI_RXBUFF) && + ((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT)); + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,AT91_SPI0_BASE + AT91_SPI_PTCR); pDesc->state = IDLE; if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) { diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 9532dd9..e1a3394 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -32,7 +32,7 @@ int usb_cpu_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ @@ -55,7 +55,7 @@ int usb_cpu_init(void) /* Enable USB host clock. */ writel(1 << ATMEL_ID_UHP, &pmc->pcer); #ifdef CONFIG_AT91SAM9261 - writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scer); + writel(ATMEl_PMC_UHP | AT91_PMC_HCK0, &pmc->scer); #else writel(ATMEL_PMC_UHP, &pmc->scer); #endif @@ -65,7 +65,7 @@ int usb_cpu_init(void) int usb_cpu_stop(void) { - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; /* Disable USB host clock. */ writel(1 << ATMEL_ID_UHP, &pmc->pcdr); diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index f6cb406..b4d8ce8 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -26,20 +26,24 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ +#define CONFIG_ARCH_CPU_INIT /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ -#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ -#define CONFIG_ARCH_CPU_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_DISPLAY_CPUINFO #ifndef CONFIG_SYS_USE_BOOT_NORFLASH #define CONFIG_SKIP_LOWLEVEL_INIT @@ -48,40 +52,44 @@ /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 +#define CONFIG_AT91_GPIO +#define CONFIG_ATMEL_USART #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART3 /* USART 3 is DBGU */ /* LCD */ -#define CONFIG_LCD 1 + +//#define CONFIG_LCD +#undef CONFIG_LCD +#ifdef CONFIG_LCD #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 +#define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_BGR555 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_LCD +#define CONFIG_ATMEL_LCD_BGR555 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* the power led */ -#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* the user1 led */ -#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 29 /* the user2 led */ +//#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* the power led */ +#define CONFIG_GREEN_LED AT91_PIO_PORTC, 4 /* the user1 led */ +#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 20 /* the user2 led */ #define CONFIG_BOOTDELAY 3 /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -94,19 +102,23 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_SOURCE -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +//#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define PHYS_SDRAM 0x20000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) +#define PHYS_SDRAM_SIZE 0x04000000 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE /* 64 megs */ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_HAS_DATAFLASH #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ @@ -252,16 +264,16 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +// #define CONFIG_NAND_ATMEL +// #define CONFIG_SYS_MAX_NAND_DEVICE 1 +// #define CONFIG_SYS_NAND_BASE 0x40000000 +// #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +// #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 +// #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +// #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +// #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 /* #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 @@ -272,32 +284,32 @@ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 +#define CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM #define CONFIG_SYS_MEMTEST_END 0x23e00000 -#ifdef CONFIG_SYS_USE_DATAFLASH +#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_ENV_IS_IN_DATAFLASH #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) -- 1.7.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot