On Fri, May 19, 2023 at 3:35 PM Adam Ford <aford...@gmail.com> wrote:
>
> On Fri, May 19, 2023 at 5:34 PM Tim Harvey <thar...@gateworks.com> wrote:
> >
> > On Fri, May 19, 2023 at 3:31 PM Tim Harvey <thar...@gateworks.com> wrote:
> > >
> > > On Fri, May 19, 2023 at 3:27 PM Adam Ford <aford...@gmail.com> wrote:
> > > >
> > > > On Fri, May 19, 2023 at 5:19 PM Tim Harvey <thar...@gateworks.com>
> > > > wrote:
> > > > >
> > > > > On Wed, May 3, 2023 at 9:11 AM Tim Harvey <thar...@gateworks.com>
> > > > > wrote:
> > > > > >
> > > > > > On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam <feste...@gmail.com>
> > > > > > wrote:
> > > > > > >
> > > > > > > From: Fabio Estevam <feste...@denx.de>
> > > > > > >
> > > > > > > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
> > > > > > >
> > > > > > > Signed-off-by: Fabio Estevam <feste...@denx.de>
> > > > > > > ---
> > > > > > > arch/arm/dts/imx8mp.dtsi | 374
> > > > > > > ++++++++++++++++-------
> > > > > > > include/dt-bindings/clock/imx8mp-clock.h | 14 +-
> > > > > > > 2 files changed, 270 insertions(+), 118 deletions(-)
> > > > > > >
> > > > > > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > > > > > > index bb916a0948a8..a237275ee017 100644
> > > > > > > --- a/arch/arm/dts/imx8mp.dtsi
> > > > > > > +++ b/arch/arm/dts/imx8mp.dtsi
> > > > > > > @@ -123,6 +123,7 @@
> > > > > > >
> > > > > > > A53_L2: l2-cache0 {
> > > > > > > compatible = "cache";
> > > > > > > + cache-unified;
> > > > > > > cache-level = <2>;
> > > > > > > cache-size = <0x80000>;
> > > > > > > cache-line-size = <64>;
> > > > > > > @@ -379,6 +380,8 @@
> > > > > > > compatible = "fsl,imx8mp-tmu";
> > > > > > > reg = <0x30260000 0x10000>;
> > > > > > > clocks = <&clk
> > > > > > > IMX8MP_CLK_TSENSOR_ROOT>;
> > > > > > > + nvmem-cells = <&tmu_calib>;
> > > > > > > + nvmem-cell-names = "calib";
> > > > > > > #thermal-sensor-cells = <1>;
> > > > > > > };
> > > > > > >
> > > > > > > @@ -411,7 +414,7 @@
> > > > > > > reg = <0x30330000 0x10000>;
> > > > > > > };
> > > > > > >
> > > > > > > - gpr: iomuxc-gpr@30340000 {
> > > > > > > + gpr: syscon@30340000 {
> > > > > > > compatible =
> > > > > > > "fsl,imx8mp-iomuxc-gpr", "syscon";
> > > > > > > reg = <0x30340000 0x10000>;
> > > > > > > };
> > > > > > > @@ -424,27 +427,44 @@
> > > > > > > #address-cells = <1>;
> > > > > > > #size-cells = <1>;
> > > > > > >
> > > > > > > - imx8mp_uid: unique-id@420 {
> > > > > > > + /*
> > > > > > > + * The register address below
> > > > > > > maps to the MX8M
> > > > > > > + * Fusemap Description Table
> > > > > > > entries this way.
> > > > > > > + * Assuming
> > > > > > > + * reg = <ADDR SIZE>;
> > > > > > > + * then
> > > > > > > + * Fuse Address = (ADDR * 4) +
> > > > > > > 0x400
> > > > > > > + * Note that if SIZE is greater
> > > > > > > than 4, then
> > > > > > > + * each subsequent fuse is
> > > > > > > located at offset
> > > > > > > + * +0x10 in Fusemap Description
> > > > > > > Table (e.g.
> > > > > > > + * reg = <0x8 0x8> describes
> > > > > > > fuses 0x420 and
> > > > > > > + * 0x430).
> > > > > > > + */
> > > > > > > + imx8mp_uid: unique-id@8 { /*
> > > > > > > 0x420-0x430 */
> > > > > > > reg = <0x8 0x8>;
> > > > > > > };
> > > > > > >
> > > > > > > - cpu_speed_grade: speed-grade@10 {
> > > > > > > + cpu_speed_grade: speed-grade@10 {
> > > > > > > /* 0x440 */
> > > > > > > reg = <0x10 4>;
> > > > > > > };
> > > > > > >
> > > > > > > - eth_mac1: mac-address@90 {
> > > > > > > + eth_mac1: mac-address@90 { /*
> > > > > > > 0x640 */
> > > > > > > reg = <0x90 6>;
> > > > > > > };
> > > > > > >
> > > > > > > - eth_mac2: mac-address@96 {
> > > > > > > + eth_mac2: mac-address@96 { /*
> > > > > > > 0x658 */
> > > > > > > reg = <0x96 6>;
> > > > > > > };
> > > > > > > +
> > > > > > > + tmu_calib: calib@264 { /*
> > > > > > > 0xd90-0xdc0 */
> > > > > > > + reg = <0x264 0x10>;
> > > > > > > + };
> > > > > > > };
> > > > > > >
> > > > > > > - anatop: anatop@30360000 {
> > > > > > > - compatible = "fsl,imx8mp-anatop",
> > > > > > > "fsl,imx8mm-anatop",
> > > > > > > - "syscon";
> > > > > > > + anatop: clock-controller@30360000 {
> > > > > > > + compatible = "fsl,imx8mp-anatop",
> > > > > > > "fsl,imx8mm-anatop";
> > > > > > > reg = <0x30360000 0x10000>;
> > > > > > > + #clock-cells = <1>;
> > > > > > > };
> > > > > > >
> > > > > > > snvs: snvs@30370000 {
> > > > > > > @@ -523,6 +543,7 @@
> > > > > > > compatible = "fsl,imx8mp-gpc";
> > > > > > > reg = <0x303a0000 0x1000>;
> > > > > > > interrupt-parent = <&gic>;
> > > > > > > + interrupts = <GIC_SPI 87
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > interrupt-controller;
> > > > > > > #interrupt-cells = <3>;
> > > > > > >
> > > > > > > @@ -589,7 +610,7 @@
> > > > > > > reg =
> > > > > > > <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
> > > > > > > };
> > > > > > >
> > > > > > > - pgc_hsiomix:
> > > > > > > power-domains@17 {
> > > > > > > + pgc_hsiomix:
> > > > > > > power-domain@17 {
> > > > > > >
> > > > > > > #power-domain-cells = <0>;
> > > > > > > reg =
> > > > > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > > > > clocks = <&clk
> > > > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > > > @@ -631,6 +652,14 @@
> > > > > > > reg =
> > > > > > > <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
> > > > > > > clocks = <&clk
> > > > > > > IMX8MP_CLK_VPU_VC8KE_ROOT>;
> > > > > > > };
> > > > > > > +
> > > > > > > + pgc_mlmix:
> > > > > > > power-domain@24 {
> > > > > > > +
> > > > > > > #power-domain-cells = <0>;
> > > > > > > + reg =
> > > > > > > <IMX8MP_POWER_DOMAIN_MLMIX>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_ML_AXI>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_ML_AHB>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_NPU_ROOT>;
> > > > > > > + };
> > > > > > > };
> > > > > > > };
> > > > > > > };
> > > > > > > @@ -702,112 +731,129 @@
> > > > > > > #size-cells = <1>;
> > > > > > > ranges;
> > > > > > >
> > > > > > > - ecspi1: spi@30820000 {
> > > > > > > + spba-bus@30800000 {
> > > > > > > + compatible = "fsl,spba-bus",
> > > > > > > "simple-bus";
> > > > > > > + reg = <0x30800000 0x100000>;
> > > > > > > #address-cells = <1>;
> > > > > > > - #size-cells = <0>;
> > > > > > > - compatible = "fsl,imx8mp-ecspi",
> > > > > > > "fsl,imx51-ecspi";
> > > > > > > - reg = <0x30820000 0x10000>;
> > > > > > > - interrupts = <GIC_SPI 31
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI1_ROOT>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_ECSPI1_ROOT>;
> > > > > > > - clock-names = "ipg", "per";
> > > > > > > - dmas = <&sdma1 0 7 1>, <&sdma1 1
> > > > > > > 7 2>;
> > > > > > > - dma-names = "rx", "tx";
> > > > > > > - status = "disabled";
> > > > > > > - };
> > > > > > > + #size-cells = <1>;
> > > > > > > + ranges;
> > > > > > >
> > > > > > > - ecspi2: spi@30830000 {
> > > > > > > - #address-cells = <1>;
> > > > > > > - #size-cells = <0>;
> > > > > > > - compatible = "fsl,imx8mp-ecspi",
> > > > > > > "fsl,imx51-ecspi";
> > > > > > > - reg = <0x30830000 0x10000>;
> > > > > > > - interrupts = <GIC_SPI 32
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI2_ROOT>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_ECSPI2_ROOT>;
> > > > > > > - clock-names = "ipg", "per";
> > > > > > > - dmas = <&sdma1 2 7 1>, <&sdma1 3
> > > > > > > 7 2>;
> > > > > > > - dma-names = "rx", "tx";
> > > > > > > - status = "disabled";
> > > > > > > - };
> > > > > > > + ecspi1: spi@30820000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
> > > > > > > + reg = <0x30820000
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 31
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI1_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_ECSPI1_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + assigned-clock-rates =
> > > > > > > <80000000>;
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI1>;
> > > > > > > + assigned-clock-parents =
> > > > > > > <&clk IMX8MP_SYS_PLL1_800M>;
> > > > > > > + dmas = <&sdma1 0 7 1>,
> > > > > > > <&sdma1 1 7 2>;
> > > > > > > + dma-names = "rx", "tx";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > >
> > > > > > > - ecspi3: spi@30840000 {
> > > > > > > - #address-cells = <1>;
> > > > > > > - #size-cells = <0>;
> > > > > > > - compatible = "fsl,imx8mp-ecspi",
> > > > > > > "fsl,imx51-ecspi";
> > > > > > > - reg = <0x30840000 0x10000>;
> > > > > > > - interrupts = <GIC_SPI 33
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI3_ROOT>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_ECSPI3_ROOT>;
> > > > > > > - clock-names = "ipg", "per";
> > > > > > > - dmas = <&sdma1 4 7 1>, <&sdma1 5
> > > > > > > 7 2>;
> > > > > > > - dma-names = "rx", "tx";
> > > > > > > - status = "disabled";
> > > > > > > - };
> > > > > > > + ecspi2: spi@30830000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
> > > > > > > + reg = <0x30830000
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 32
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI2_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_ECSPI2_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + assigned-clock-rates =
> > > > > > > <80000000>;
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI2>;
> > > > > > > + assigned-clock-parents =
> > > > > > > <&clk IMX8MP_SYS_PLL1_800M>;
> > > > > > > + dmas = <&sdma1 2 7 1>,
> > > > > > > <&sdma1 3 7 2>;
> > > > > > > + dma-names = "rx", "tx";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > >
> > > > > > > - uart1: serial@30860000 {
> > > > > > > - compatible = "fsl,imx8mp-uart",
> > > > > > > "fsl,imx6q-uart";
> > > > > > > - reg = <0x30860000 0x10000>;
> > > > > > > - interrupts = <GIC_SPI 26
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_UART1_ROOT>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_UART1_ROOT>;
> > > > > > > - clock-names = "ipg", "per";
> > > > > > > - dmas = <&sdma1 22 4 0>, <&sdma1
> > > > > > > 23 4 0>;
> > > > > > > - dma-names = "rx", "tx";
> > > > > > > - status = "disabled";
> > > > > > > - };
> > > > > > > + ecspi3: spi@30840000 {
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
> > > > > > > + reg = <0x30840000
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 33
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI3_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_ECSPI3_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + assigned-clock-rates =
> > > > > > > <80000000>;
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_ECSPI3>;
> > > > > > > + assigned-clock-parents =
> > > > > > > <&clk IMX8MP_SYS_PLL1_800M>;
> > > > > > > + dmas = <&sdma1 4 7 1>,
> > > > > > > <&sdma1 5 7 2>;
> > > > > > > + dma-names = "rx", "tx";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > >
> > > > > > > - uart3: serial@30880000 {
> > > > > > > - compatible = "fsl,imx8mp-uart",
> > > > > > > "fsl,imx6q-uart";
> > > > > > > - reg = <0x30880000 0x10000>;
> > > > > > > - interrupts = <GIC_SPI 28
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_UART3_ROOT>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_UART3_ROOT>;
> > > > > > > - clock-names = "ipg", "per";
> > > > > > > - dmas = <&sdma1 26 4 0>, <&sdma1
> > > > > > > 27 4 0>;
> > > > > > > - dma-names = "rx", "tx";
> > > > > > > - status = "disabled";
> > > > > > > - };
> > > > > > > + uart1: serial@30860000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-uart", "fsl,imx6q-uart";
> > > > > > > + reg = <0x30860000
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 26
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_UART1_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_UART1_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + dmas = <&sdma1 22 4 0>,
> > > > > > > <&sdma1 23 4 0>;
> > > > > > > + dma-names = "rx", "tx";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > >
> > > > > > > - uart2: serial@30890000 {
> > > > > > > - compatible = "fsl,imx8mp-uart",
> > > > > > > "fsl,imx6q-uart";
> > > > > > > - reg = <0x30890000 0x10000>;
> > > > > > > - interrupts = <GIC_SPI 27
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_UART2_ROOT>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_UART2_ROOT>;
> > > > > > > - clock-names = "ipg", "per";
> > > > > > > - dmas = <&sdma1 24 4 0>, <&sdma1
> > > > > > > 25 4 0>;
> > > > > > > - dma-names = "rx", "tx";
> > > > > > > - status = "disabled";
> > > > > > > - };
> > > > > > > + uart3: serial@30880000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-uart", "fsl,imx6q-uart";
> > > > > > > + reg = <0x30880000
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 28
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_UART3_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_UART3_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + dmas = <&sdma1 26 4 0>,
> > > > > > > <&sdma1 27 4 0>;
> > > > > > > + dma-names = "rx", "tx";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > >
> > > > > > > - flexcan1: can@308c0000 {
> > > > > > > - compatible = "fsl,imx8mp-flexcan";
> > > > > > > - reg = <0x308c0000 0x10000>;
> > > > > > > - interrupts = <GIC_SPI 142
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_IPG_ROOT>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_CAN1_ROOT>;
> > > > > > > - clock-names = "ipg", "per";
> > > > > > > - assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_CAN1>;
> > > > > > > - assigned-clock-parents = <&clk
> > > > > > > IMX8MP_SYS_PLL1_40M>;
> > > > > > > - assigned-clock-rates = <40000000>;
> > > > > > > - fsl,clk-source = /bits/ 8 <0>;
> > > > > > > - fsl,stop-mode = <&gpr 0x10 4>;
> > > > > > > - status = "disabled";
> > > > > > > - };
> > > > > > > + uart2: serial@30890000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-uart", "fsl,imx6q-uart";
> > > > > > > + reg = <0x30890000
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 27
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_UART2_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_UART2_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + dmas = <&sdma1 24 4 0>,
> > > > > > > <&sdma1 25 4 0>;
> > > > > > > + dma-names = "rx", "tx";
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > >
> > > > > > > - flexcan2: can@308d0000 {
> > > > > > > - compatible = "fsl,imx8mp-flexcan";
> > > > > > > - reg = <0x308d0000 0x10000>;
> > > > > > > - interrupts = <GIC_SPI 144
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_IPG_ROOT>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_CAN2_ROOT>;
> > > > > > > - clock-names = "ipg", "per";
> > > > > > > - assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_CAN2>;
> > > > > > > - assigned-clock-parents = <&clk
> > > > > > > IMX8MP_SYS_PLL1_40M>;
> > > > > > > - assigned-clock-rates = <40000000>;
> > > > > > > - fsl,clk-source = /bits/ 8 <0>;
> > > > > > > - fsl,stop-mode = <&gpr 0x10 5>;
> > > > > > > - status = "disabled";
> > > > > > > + flexcan1: can@308c0000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-flexcan";
> > > > > > > + reg = <0x308c0000
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 142
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_IPG_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_CAN1_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_CAN1>;
> > > > > > > + assigned-clock-parents =
> > > > > > > <&clk IMX8MP_SYS_PLL1_40M>;
> > > > > > > + assigned-clock-rates =
> > > > > > > <40000000>;
> > > > > > > + fsl,clk-source = /bits/ 8
> > > > > > > <0>;
> > > > > > > + fsl,stop-mode = <&gpr
> > > > > > > 0x10 4>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > +
> > > > > > > + flexcan2: can@308d0000 {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-flexcan";
> > > > > > > + reg = <0x308d0000
> > > > > > > 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 144
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_IPG_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_CAN2_ROOT>;
> > > > > > > + clock-names = "ipg",
> > > > > > > "per";
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_CAN2>;
> > > > > > > + assigned-clock-parents =
> > > > > > > <&clk IMX8MP_SYS_PLL1_40M>;
> > > > > > > + assigned-clock-rates =
> > > > > > > <40000000>;
> > > > > > > + fsl,clk-source = /bits/ 8
> > > > > > > <0>;
> > > > > > > + fsl,stop-mode = <&gpr
> > > > > > > 0x10 5>;
> > > > > > > + status = "disabled";
> > > > > > > + };
> > > > > > > };
> > > > > > >
> > > > > > > crypto: crypto@30900000 {
> > > > > > > @@ -1063,11 +1109,11 @@
> > > > > > > noc_opp_table: opp-table {
> > > > > > > compatible =
> > > > > > > "operating-points-v2";
> > > > > > >
> > > > > > > - opp-200M {
> > > > > > > + opp-200000000 {
> > > > > > > opp-hz = /bits/ 64
> > > > > > > <200000000>;
> > > > > > > };
> > > > > > >
> > > > > > > - opp-1000M {
> > > > > > > + opp-1000000000 {
> > > > > > > opp-hz = /bits/ 64
> > > > > > > <1000000000>;
> > > > > > > };
> > > > > > > };
> > > > > > > @@ -1080,10 +1126,35 @@
> > > > > > > #size-cells = <1>;
> > > > > > > ranges;
> > > > > > >
> > > > > > > + lcdif2: display-controller@32e90000 {
> > > > > > > + compatible = "fsl,imx8mp-lcdif";
> > > > > > > + reg = <0x32e90000 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 6
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_MEDIA_APB_ROOT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_MEDIA_AXI_ROOT>;
> > > > > > > + clock-names = "pix", "axi",
> > > > > > > "disp_axi";
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_MEDIA_DISP2_PIX>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_VIDEO_PLL1>;
> > > > > > > + assigned-clock-parents = <&clk
> > > > > > > IMX8MP_VIDEO_PLL1_OUT>,
> > > > > > > + <&clk
> > > > > > > IMX8MP_VIDEO_PLL1_REF_SEL>;
> > > > > > > + assigned-clock-rates = <0>,
> > > > > > > <1039500000>;
> > > > > > > + power-domains = <&media_blk_ctrl
> > > > > > > IMX8MP_MEDIABLK_PD_LCDIF_2>;
> > > > > > > + status = "disabled";
> > > > > > > +
> > > > > > > + port {
> > > > > > > + lcdif2_to_ldb: endpoint {
> > > > > > > + remote-endpoint =
> > > > > > > <&ldb_from_lcdif2>;
> > > > > > > + };
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > media_blk_ctrl: blk-ctrl@32ec0000 {
> > > > > > > compatible =
> > > > > > > "fsl,imx8mp-media-blk-ctrl",
> > > > > > > - "syscon";
> > > > > > > + "simple-bus",
> > > > > > > "syscon";
> > > > > > > reg = <0x32ec0000 0x10000>;
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <1>;
> > > > > > > power-domains = <&pgc_mediamix>,
> > > > > > > <&pgc_mipi_phy1>,
> > > > > > > <&pgc_mipi_phy1>,
> > > > > > > @@ -1128,6 +1199,44 @@
> > > > > > > assigned-clock-rates =
> > > > > > > <500000000>, <200000000>;
> > > > > > >
> > > > > > > #power-domain-cells = <1>;
> > > > > > > +
> > > > > > > + lvds_bridge: bridge@5c {
> > > > > > > + compatible =
> > > > > > > "fsl,imx8mp-ldb";
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_MEDIA_LDB>;
> > > > > > > + clock-names = "ldb";
> > > > > > > + reg = <0x5c 0x4>, <0x128
> > > > > > > 0x4>;
> > > > > > > + reg-names = "ldb", "lvds";
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_MEDIA_LDB>;
> > > > > > > + assigned-clock-parents =
> > > > > > > <&clk IMX8MP_VIDEO_PLL1_OUT>;
> > > > > > > + status = "disabled";
> > > > > > > +
> > > > > > > + ports {
> > > > > > > + #address-cells =
> > > > > > > <1>;
> > > > > > > + #size-cells = <0>;
> > > > > > > +
> > > > > > > + port@0 {
> > > > > > > + reg = <0>;
> > > > > > > +
> > > > > > > +
> > > > > > > ldb_from_lcdif2: endpoint {
> > > > > > > +
> > > > > > > remote-endpoint = <&lcdif2_to_ldb>;
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + port@1 {
> > > > > > > + reg = <1>;
> > > > > > > +
> > > > > > > +
> > > > > > > ldb_lvds_ch0: endpoint {
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + port@2 {
> > > > > > > + reg = <2>;
> > > > > > > +
> > > > > > > +
> > > > > > > ldb_lvds_ch1: endpoint {
> > > > > > > + };
> > > > > > > + };
> > > > > > > + };
> > > > > > > + };
> > > > > > > };
> > > > > > >
> > > > > > > pcie_phy: pcie-phy@32f00000 {
> > > > > > > @@ -1158,6 +1267,7 @@
> > > > > > > <&noc
> > > > > > > IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
> > > > > > > interconnect-names = "noc-pcie",
> > > > > > > "usb1", "usb2", "pcie";
> > > > > > > #power-domain-cells = <1>;
> > > > > > > + #clock-cells = <0>;
> > > > > > > };
> > > > > > > };
> > > > > > >
> > > > > > > @@ -1165,6 +1275,13 @@
> > > > > > > compatible = "fsl,imx8mp-pcie";
> > > > > > > reg = <0x33800000 0x400000>, <0x1ff00000
> > > > > > > 0x80000>;
> > > > > > > reg-names = "dbi", "config";
> > > > > > > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> > > > > > > + <&clk IMX8MP_CLK_HSIO_AXI>,
> > > > > > > + <&clk IMX8MP_CLK_PCIE_ROOT>;
> > > > > > > + clock-names = "pcie", "pcie_bus",
> > > > > > > "pcie_aux";
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_PCIE_AUX>;
> > > > > > > + assigned-clock-rates = <10000000>;
> > > > > > > + assigned-clock-parents = <&clk
> > > > > > > IMX8MP_SYS_PLL2_50M>;
> > > > > > > #address-cells = <3>;
> > > > > > > #size-cells = <2>;
> > > > > > > device_type = "pci";
> > > > > > > @@ -1223,6 +1340,28 @@
> > > > > > > power-domains = <&pgc_gpu2d>;
> > > > > > > };
> > > > > > >
> > > > > > > + vpu_g1: video-codec@38300000 {
> > > > > > > + compatible = "nxp,imx8mm-vpu-g1";
> > > > > > > + reg = <0x38300000 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 7
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_VPU_G1>;
> > > > > > > + assigned-clock-parents = <&clk
> > > > > > > IMX8MP_VPU_PLL_OUT>;
> > > > > > > + assigned-clock-rates = <600000000>;
> > > > > > > + power-domains = <&vpumix_blk_ctrl
> > > > > > > IMX8MP_VPUBLK_PD_G1>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + vpu_g2: video-codec@38310000 {
> > > > > > > + compatible = "nxp,imx8mq-vpu-g2";
> > > > > > > + reg = <0x38310000 0x10000>;
> > > > > > > + interrupts = <GIC_SPI 8
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_VPU_G2>;
> > > > > > > + assigned-clock-parents = <&clk
> > > > > > > IMX8MP_SYS_PLL2_1000M>;
> > > > > > > + assigned-clock-rates = <500000000>;
> > > > > > > + power-domains = <&vpumix_blk_ctrl
> > > > > > > IMX8MP_VPUBLK_PD_G2>;
> > > > > > > + };
> > > > > > > +
> > > > > > > vpumix_blk_ctrl: blk-ctrl@38330000 {
> > > > > > > compatible = "fsl,imx8mp-vpu-blk-ctrl",
> > > > > > > "syscon";
> > > > > > > reg = <0x38330000 0x100>;
> > > > > > > @@ -1234,6 +1373,9 @@
> > > > > > > <&clk IMX8MP_CLK_VPU_G2_ROOT>,
> > > > > > > <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
> > > > > > > clock-names = "g1", "g2", "vc8000e";
> > > > > > > + assigned-clocks = <&clk
> > > > > > > IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
> > > > > > > + assigned-clock-parents = <&clk
> > > > > > > IMX8MP_VPU_PLL_OUT>;
> > > > > > > + assigned-clock-rates = <600000000>,
> > > > > > > <600000000>;
> > > > > > > interconnects = <&noc IMX8MP_ICM_VPU_G1
> > > > > > > &noc IMX8MP_ICN_VIDEO>,
> > > > > > > <&noc IMX8MP_ICM_VPU_G2
> > > > > > > &noc IMX8MP_ICN_VIDEO>,
> > > > > > > <&noc IMX8MP_ICM_VPU_H1
> > > > > > > &noc IMX8MP_ICN_VIDEO>;
> > > > > > > @@ -1279,7 +1421,7 @@
> > > > > > > reg = <0x32f10100 0x8>,
> > > > > > > <0x381f0000 0x20>;
> > > > > > > clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> > > > > > > - <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > > > + <&clk IMX8MP_CLK_USB_SUSP>;
> > > > > > > clock-names = "hsio", "suspend";
> > > > > > > interrupts = <GIC_SPI 148
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > power-domains = <&hsio_blk_ctrl
> > > > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > > > @@ -1292,9 +1434,9 @@
> > > > > > > usb_dwc3_0: usb@38100000 {
> > > > > > > compatible = "snps,dwc3";
> > > > > > > reg = <0x38100000 0x10000>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_USB_ROOT>,
> > > > > > > <&clk
> > > > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_USB_SUSP>;
> > > > > > > clock-names = "bus_early", "ref",
> > > > > > > "suspend";
> > > > > > > interrupts = <GIC_SPI 40
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > phys = <&usb3_phy0>, <&usb3_phy0>;
> > > > > > > @@ -1321,7 +1463,7 @@
> > > > > > > reg = <0x32f10108 0x8>,
> > > > > > > <0x382f0000 0x20>;
> > > > > > > clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> > > > > > > - <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > > > + <&clk IMX8MP_CLK_USB_SUSP>;
> > > > > > > clock-names = "hsio", "suspend";
> > > > > > > interrupts = <GIC_SPI 149
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > power-domains = <&hsio_blk_ctrl
> > > > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > > > @@ -1334,9 +1476,9 @@
> > > > > > > usb_dwc3_1: usb@38200000 {
> > > > > > > compatible = "snps,dwc3";
> > > > > > > reg = <0x38200000 0x10000>;
> > > > > > > - clocks = <&clk
> > > > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > > > + clocks = <&clk
> > > > > > > IMX8MP_CLK_USB_ROOT>,
> > > > > > > <&clk
> > > > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > > > - <&clk
> > > > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > > > + <&clk
> > > > > > > IMX8MP_CLK_USB_SUSP>;
> > > > > > > clock-names = "bus_early", "ref",
> > > > > > > "suspend";
> > > > > > > interrupts = <GIC_SPI 41
> > > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > > phys = <&usb3_phy1>, <&usb3_phy1>;
> > > > > > > diff --git a/include/dt-bindings/clock/imx8mp-clock.h
> > > > > > > b/include/dt-bindings/clock/imx8mp-clock.h
> > > > > > > index 9d5cc2ddde89..3f28ce685f41 100644
> > > > > > > --- a/include/dt-bindings/clock/imx8mp-clock.h
> > > > > > > +++ b/include/dt-bindings/clock/imx8mp-clock.h
> > > > > > > @@ -324,8 +324,18 @@
> > > > > > > #define IMX8MP_CLK_CLKOUT2_SEL 317
> > > > > > > #define IMX8MP_CLK_CLKOUT2_DIV 318
> > > > > > > #define IMX8MP_CLK_CLKOUT2 319
> > > > > > > -
> > > > > > > -#define IMX8MP_CLK_END 320
> > > > > > > +#define IMX8MP_CLK_USB_SUSP 320
> > > > > > > +#define IMX8MP_CLK_AUDIO_AHB_ROOT
> > > > > > > IMX8MP_CLK_AUDIO_ROOT
> > > > > > > +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321
> > > > > > > +#define IMX8MP_CLK_SAI1_ROOT 322
> > > > > > > +#define IMX8MP_CLK_SAI2_ROOT 323
> > > > > > > +#define IMX8MP_CLK_SAI3_ROOT 324
> > > > > > > +#define IMX8MP_CLK_SAI5_ROOT 325
> > > > > > > +#define IMX8MP_CLK_SAI6_ROOT 326
> > > > > > > +#define IMX8MP_CLK_SAI7_ROOT 327
> > > > > > > +#define IMX8MP_CLK_PDM_ROOT 328
> > > > > > > +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329
> > > > > > > +#define IMX8MP_CLK_END 330
> > > > > > >
> > > > > > > #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
> > > > > > > #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
> > > > > > > --
> > > > > > > 2.34.1
> > > > > > >
> > > > > >
> > > > > > Tested-by: Tim Harvey <thar...@gateworks.com> #imx8mp-venice-gw74xx
> > > > >
> > > > > Fabio,
> > > > >
> > > > > Apparently I didn't do a very good job of testing this. This patch is
> > > > > causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with
> > > > > no SPL banner. The specific change that causes breakage is the one
> > > > > that encapsulates the spi/uart/flexcan children with
> > > > > spba-bus@30800000.
> > > >
> > > > The SPI, UART, and Flexcan are part of the spba-bus.
> > > >
> > > > We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no
> > > > node name, it'll have to fall under aip3.
> > > >
> > > > Try this:
> > > >
> > > > diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi
> > > > b/arch/arm/dts/imx8mp-u-boot.dtsi
> > > > index 18d1728e1d..0e6811b129 100644
> > > > --- a/arch/arm/dts/imx8mp-u-boot.dtsi
> > > > +++ b/arch/arm/dts/imx8mp-u-boot.dtsi
> > > > @@ -44,6 +44,10 @@
> > > >
> > > > &aips3 {
> > > > bootph-pre-ram;
> > > > +
> > > > + spba-bus@30800000 {
> > > > + bootph-pre-ram;
> > > > + };
> > > > };
> > > >
> > > > &iomuxc {
> > > >
> > >
> > > Adam,
> > >
> > > Yup... that's it! Thanks. Want to send a patch or want me to do it?
> > >
> >
> > Actually Fabio I think you should re-submit this patch with the
> > required change to imx8mp-u-boot.dtsi included?
>
> I was just about to say the same thing.
>
Fabio,
There's more to be done here also. With this patch, and with the
spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
you get:
starting USB...
Bus usb@38200000:
Enable clock-controller@30380000 failed
probe failed, error -2
No working controllers found
So until we get this figured out please don't apply this.
Best Regards,
Tim
