Hello Stefano,
Stefano Babic wrote:
> On 01/21/2011 07:36 AM, Heiko Schocher wrote:
>>> +static int wait_complete(void)
>>> +{
>>> + int timeout = I2C_MAX_TIMEOUT;
>>> +
>>> + while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) {
>>> + writew(0, I2C_BASE + I2SR);
>>> + udelay(1);
>>> + }
>>> + udelay(200);
>> Why is this delay necessary? Why exactly 200? Is this documented
>> somewhere in the doc?
>
> Rather I do not have a clear explanation. In the manual there is a hint
> regarding a delay that SW must introduce after setting the RSTA bit and
> before writing data into the I2DR register. Really this delay should be
> very short, but I checked removing the udelay() or decreasing the value
> to some uSec and it does not work.
>
> This is the output with debugging after removing the udelay call:
>
> i2c_read chip: 0x08 addr: 0x0007 alen: 1 len: 3
> i2c_addr:chip address cycle fail(a1)
> i2c_addr failed
> i2c_read chip: 0x08 addr: 0x001e alen: 1 len: 3
> i2c_addr:chip address cycle fail(a1)
> i2c_addr failed
>
> This happens in the i2_read() call, and it is the function where the
> RSTA bit is set. I can only presume the two things are related.
> I checked then with the driver provided by Freescale in the LTIB, and
> also in this driver a delay is set after checking transfer is completed.
Thanks for the explanation, so:
Acked-by: Heiko Schocher <h...@denx.de>
bye,
Heiko
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