If the UART bus or baud clock has a gate, it must be enabled before the
UART can be used.
Reviewed-by: Stefan Roese <s...@denx.de>
Signed-off-by: Samuel Holland <sam...@sholland.org>
---
Changes in v3:
- Switch back to the original patch, now that the phycore-rk3288 build
is fixed by enabling LTO in patch 1.
Changes in v2:
- Only enable the first clock, as using the clk_get_bulk() API pushes
a board (phycore-rk3288) over its SPL size limit.
drivers/serial/ns16550.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index eab9537fba..50ec36ed7f 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -506,6 +506,7 @@ int ns16550_serial_probe(struct udevice *dev)
struct ns16550_plat *plat = dev_get_plat(dev);
struct ns16550 *const com_port = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
+ struct clk_bulk clk_bulk;
fdt_addr_t addr;
int ret;
@@ -524,6 +525,10 @@ int ns16550_serial_probe(struct udevice *dev)
if (!ret)
reset_deassert_bulk(&reset_bulk);
+ ret = clk_get_bulk(dev, &clk_bulk);
+ if (!ret)
+ clk_enable_bulk(&clk_bulk);
+
com_port->plat = dev_get_plat(dev);
ns16550_init(com_port, -1);
--
2.37.4
