Hi Benjamin,

On Sun, Dec 18, 2022 at 9:52 AM <egyszer...@freemail.hu> wrote:
>
> From: Benjamin Szőke <egyszer...@freemail.hu>
>
> Take over codes from Techenxion to support SoMs with 2GB DDR3.
>
> Signed-off-by: Benjamin Szőke <egyszer...@freemail.hu>
> ---
>  board/technexion/pico-imx7d/Makefile          |  2 +-
>  .../pico-imx7d/{spl.c => pico-imx7d_spl.c}    | 30 +++++++++++++++++--
>  2 files changed, 28 insertions(+), 4 deletions(-)
>  rename board/technexion/pico-imx7d/{spl.c => pico-imx7d_spl.c} (83%)

Could you please test whether the attached patch works for you?

I don't have a 2GB board variant here to test it myself.

You also need to apply the following patch to fix the boot against
U-Boot top of tree:
https://lore.kernel.org/u-boot/20221231162514.334303-1-feste...@denx.de/T/#u
From 1777fa36f9b1e93284969b49037daa3871e99a77 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <feste...@denx.de>
Date: Sat, 31 Dec 2022 13:14:02 -0300
Subject: [PATCH] pico-imx7d: Add support for the 2GB variant

Add the board detection mechanism to be able to support
the 2GB variant.

Based on the code from TechNexion U-Boot downstream tree.

Signed-off-by: Fabio Estevam <feste...@denx.de>
---
 board/technexion/pico-imx7d/spl.c | 30 +++++++++++++++++++++++++++---
 1 file changed, 27 insertions(+), 3 deletions(-)

diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c
index df5f058577..f86fee9c88 100644
--- a/board/technexion/pico-imx7d/spl.c
+++ b/board/technexion/pico-imx7d/spl.c
@@ -61,6 +61,8 @@ static struct ddrc ddrc_regs_val = {
 	.dramtmg0	= 0x09081109,
 	.addrmap0	= 0x0000001f,
 	.addrmap1	= 0x00080808,
+	.addrmap2	= 0x00000000,
+	.addrmap3	= 0x00000000,
 	.addrmap4	= 0x00000f0f,
 	.addrmap5	= 0x07070707,
 	.addrmap6	= 0x0f0f0707,
@@ -100,16 +102,38 @@ static void gpr_init(void)
 	writel(0x4F400005, &gpr_regs->gpr[1]);
 }
 
-static bool is_1g(void)
+/*
+ * Revision Detection
+ *
+ *   GPIO1_12           GPIO1_13
+ *     0                0           1GB DDR3
+ *     0                1           2GB DDR3
+ *     1                0           512MB DDR3
+ */
+
+static int imx7d_pico_detect_board(void)
 {
 	gpio_direction_input(IMX_GPIO_NR(1, 12));
-	return !gpio_get_value(IMX_GPIO_NR(1, 12));
+	gpio_direction_input(IMX_GPIO_NR(1, 13));
+
+	return gpio_get_value(IMX_GPIO_NR(1, 12)) << 1 |
+	       gpio_get_value(IMX_GPIO_NR(1, 13));
 }
 
 static void ddr_init(void)
 {
-	if (is_1g())
+	switch (imx7d_pico_detect_board()) {
+	case 0:
 		ddrc_regs_val.addrmap6	= 0x0f070707;
+		break;
+	case 1:
+		ddrc_regs_val.addrmap0	= 0x0000001f;
+		ddrc_regs_val.addrmap1	= 0x00181818;
+		ddrc_regs_val.addrmap4	= 0x00000f0f;
+		ddrc_regs_val.addrmap5	= 0x04040404;
+		ddrc_regs_val.addrmap6	= 0x04040404;
+		break;
+	}
 
 	mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
 		     &calib_param);
-- 
2.25.1

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