---
board/eNET/eNET.c | 64 +++++++++++++++++++++++++++++++++++++----------
include/configs/eNET.h | 31 +++++++++++++++++++++-
2 files changed, 79 insertions(+), 16 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index b4ef183..db3be5f 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -47,6 +47,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
static void enet_timer_isr(void);
static void enet_toggle_run_led(void);
+static void enet_setup_pars(void);
/*
* Miscellaneous platform dependent initializations
@@ -69,20 +70,7 @@ int board_early_init_f(void)
writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function
15-0 reg */
writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin
Function Select */
- writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
- writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
- writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
- writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
- writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
- writel(CONFIG_SYS_SC520_STRATA_FLASH1_PAR, &sc520_mmcr->par[7]);
- writel(CONFIG_SYS_SC520_STRATA_FLASH2_PAR, &sc520_mmcr->par[8]);
- writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]);
- writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]);
- writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]);
- writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]);
- writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]);
-/* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */
-/* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
+ enet_setup_pars();
/* Disable Watchdog */
writew(0x3333, &sc520_mmcr->wdtmrctl);
@@ -112,6 +100,54 @@ int board_early_init_f(void)
return 0;
}
+static void enet_setup_pars(void)
+{
+ /*
+ * PARs 11 and 12 are 2MB SRAM @ 0x19000000
+ *
+ * These are setup now because older version of U-Boot have them
+ * mapped to a different PAR which gets clobbered which prevents
+ * using SRAM for warm-booting a new image
+ */
+ writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
+ writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
+
+ /* PARs 0 and 1 are Compact Flash slots (4kB each) */
+ writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
+ writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
+
+ /* PAR 2 is used for Cache-As-RAM */
+
+ /* PARs 3 and 4 are SDRAM */
+ writel(SC520_SDRAM1_PAR, &sc520_mmcr->par[3]);
+ writel(SC520_SDRAM2_PAR, &sc520_mmcr->par[4]);
+
+ /*
+ * PARs 5 through 8 are additional NS16550 UARTS
+ * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
+ */
+ writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
+ writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
+ writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
+ writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
+
+ /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
+ writel(CONFIG_SYS_SC520_STRATA_FLASH1_PAR, &sc520_mmcr->par[9]);
+ writel(CONFIG_SYS_SC520_STRATA_FLASH2_PAR, &sc520_mmcr->par[10]);
+
+ /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
+ writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
+
+ /*
+ * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
+ * Already configured in board_init16 (eNET_start16.S)
+ *
+ * PAR 15 is Boot ROM
+ * Already configured in board_init16 (eNET_start16.S)
+ */
+}
+
+
int board_early_init_r(void)
{
/* CPU Speed to 100MHz */
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index de73434..9ad10de 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -341,8 +341,35 @@
/* Dual-Port RAM - 4kB @ 0x18100000 on GPCS4 */
#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
-/* SDRAM - 128MB @ 0x00000000 */
-#define CONFIG_SYS_SC520_SDRAM_PAR 0xe3ffc000
+/*
+ * First 128MB of SDRAM RAM
+ *
+ * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x00000000
+ * | | | | | +----------------------- 128MB Region Size ((2047 + 1) *
64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Enabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- SDRAM
+ */
+#define SC520_SDRAM1_PAR 0xe3ffc000
+
+/*
+ * Second 128MB of SDRAM RAM
+ *
+ * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x08000000
+ * | | | | | +----------------------- 128MB Region Size ((2047 + 1) *
64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Disabled
+ * +--------------------------------------- SDRAM
+ */
+#define SC520_SDRAM2_PAR 0xe3ffc800
#ifndef __ASSEMBLER__
extern unsigned long ip;
--
1.7.1.422.g049e9
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