---
board/eNET/eNET.c | 28 ++++++++++----------
board/eNET/eNET_start16.S | 6 ++--
include/configs/eNET.h | 61 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+), 17 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index fa10c6e..b4ef183 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -69,20 +69,20 @@ int board_early_init_f(void)
writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function
15-0 reg */
writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin
Function Select */
- writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0,
0x013f8, 8 Bytes) */
- writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3,
0x012f8, 8 Bytes) */
- writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4,
0x011f8, 8 Bytes) */
- writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5,
0x010f8, 8 Bytes) */
- writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000,
128MB) */
- writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1,
0x10000000, 16MB) */
- writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2,
0x11000000, 16MB) */
- writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0,
0x19000000, 1MB) */
- writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3,
0x19100000, 1MB) */
- writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4,
0x18100000, 4kB) */
- writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1
(0x200000000, 4kB) */
- writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2
(0x200010000, 4kB) */
-/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at
0x18000000 */
-/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6,
0x1000, 20 Bytes */
+ writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
+ writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
+ writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
+ writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
+ writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
+ writel(CONFIG_SYS_SC520_STRATA_FLASH1_PAR, &sc520_mmcr->par[7]);
+ writel(CONFIG_SYS_SC520_STRATA_FLASH2_PAR, &sc520_mmcr->par[8]);
+ writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]);
+ writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]);
+ writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]);
+ writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]);
+ writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]);
+/* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */
+/* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
/* Disable Watchdog */
writew(0x3333, &sc520_mmcr->wdtmrctl);
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
index 183309c..6db72ee 100644
--- a/board/eNET/eNET_start16.S
+++ b/board/eNET/eNET_start16.S
@@ -28,7 +28,7 @@
*/
/* #include <asm/ic/sc520_defs.h> */
-
+#include "config.h"
#include "hardware.h"
#include <asm/ic/sc520.h>
@@ -48,12 +48,12 @@ board_init16:
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi
- movl $0x8bfff800, %eax /* TODO: Check this */
+ movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi
- movl $0x38201000, %eax
+ movl $CONFIG_SYS_SC520_LLIO_PAR, %eax
movl %eax, (%di)
/* Disable SDRAM write buffer */
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 4e96a3a..de73434 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -283,6 +283,67 @@
#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
+/*-----------------------------------------------------------------------
+ * Programmable Address Region (PAR) configuration
+ */
+
+/*
+ * PAR for Boot Flash (BOOTCS, 512kB @ 0x38000000)
+ *
+ * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x38000000
+ * | | | | | +----------------------- 512kB Region Size ((7 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled (So it can be
reprogrammed!)
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8bfff800
+
+/*
+ * PAR for Low Level I/O (LEDs, Hex Switches etc) (GPCS6, 33 Bytes @ 0x1000)
+ *
+ * 001 110 0 000100000 0001000000000000 }- 0x38201000
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x00001000
+ * | | | +------------------------ 33 Bytes (0x20 + 1)
+ * | | +------------------------------ Ignored
+ * | |
+ * | |
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
+
+/* Compact Flash Ports - 4kB @ 0x200000000 (CF1) & 0x200010000 (CF2) */
+#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
+#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
+
+/*
+ * Extra 16550 UARTs - 8 bytes @ 0x013f8 (GPCS0), 0x012f8 (GPCS3),
+ * 0x011f8 (GPCS4) & 0x010f8 (GPCS5)
+ */
+#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
+#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
+#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
+#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
+
+/* StrataFlash - 16MB @ 0x10000000 (ROMCS1) & 16MB @ 0x11000000 (ROMCS2) */
+#define CONFIG_SYS_SC520_STRATA_FLASH1_PAR 0xaa3fd000
+#define CONFIG_SYS_SC520_STRATA_FLASH2_PAR 0xca3fd100
+
+/* SRAM1MB @ 0x19000000 (GPCS0) & 1MB @ 0x19100000 (GPCS3)*/
+#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
+#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
+
+/* Dual-Port RAM - 4kB @ 0x18100000 on GPCS4 */
+#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
+
+/* SDRAM - 128MB @ 0x00000000 */
+#define CONFIG_SYS_SC520_SDRAM_PAR 0xe3ffc000
+
#ifndef __ASSEMBLER__
extern unsigned long ip;
--
1.7.1.422.g049e9
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