st 31. 8. 2022 v 11:29 odesÃlatel Michal Simek <michal.si...@amd.com> napsal: > > The main reason is that DT memory reserved code is expecting DT to be 64bit > aligned. For more information take a look at commit 5bd5ee02b23b ("xilinx: > zynqmp: Check that DT is 64bit aligned"). > > Signed-off-by: Michal Simek <michal.si...@amd.com> > --- > > arch/arm/mach-zynq/u-boot.lds | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds > index a5169fd9150e..3b7c9d515f8b 100644 > --- a/arch/arm/mach-zynq/u-boot.lds > +++ b/arch/arm/mach-zynq/u-boot.lds > @@ -75,7 +75,7 @@ SECTIONS > *(.__efi_runtime_rel_stop) > } > > - . = ALIGN(4); > + . = ALIGN(8); > .image_copy_end : > { > *(.__image_copy_end) > @@ -114,7 +114,7 @@ SECTIONS > > .bss __bss_base (OVERLAY) : { > *(.bss*) > - . = ALIGN(4); > + . = ALIGN(8); > __bss_limit = .; > } > > -- > 2.36.1 >
Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs