Am Freitag, 28. Januar 2022, 14:47:13 CEST schrieb Alexandre Ghiti: > The following description is copied from the equivalent patch for the > Linux Kernel proposed by Aurelien Jarno: > > From version 2.38, binutils default to ISA spec version 20191213. This > means that the csr read/write (csrr*/csrw*) instructions and fence.i > instruction has separated from the `I` extension, become two standalone > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > this causes the following build failure: > > arch/riscv/cpu/mtrap.S: Assembler messages: > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' > > Signed-off-by: Alexandre Ghiti <alexandre.gh...@canonical.com>
After upgrading my binutils to the recent snapshot package in Debian-unstable (2.38.50.20220622-1), I've also run into that issue: /home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/drivers/timer/riscv_timer.c: Assembler messages: /home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/drivers/timer/riscv_timer.c:24: Error: unrecognized opcode `csrr a0,0xc01', extension `zicsr' required make[3]: *** [/home/devel/hstuebner/04_riscv/sun20i_d1_u-boot/scripts/Makefile.build:254: drivers/timer/riscv_timer.o] Fehler 1 Is there progress in getting this patch applied to u-boot in some way? Also it looks like there was another patch with similar content submitted recently [0]. In any case: On a D1-Nezha it fixes the build (and boot) Tested-by: Heiko Stuebner <he...@sntech.de> Thanks Heiko [0] https://lore.kernel.org/all/ph7pr14mb5594fd11d1be74284f554bebce...@ph7pr14mb5594.namprd14.prod.outlook.com/ > --- > arch/riscv/Makefile | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 0b80eb8d86..53d1194ffb 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) > CMODEL = medany > endif > > -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ > +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) > + > +# Newer binutils versions default to ISA spec version 20191213 which moves > some > +# instructions from the I extension to the Zicsr and Zifencei extensions. > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) > -march=$(RISCV_MARCH)_zicsr_zifencei) > +ifeq ($(toolchain-need-zicsr-zifencei),y) > + RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei > +endif > + > +ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ > -mcmodel=$(CMODEL) > > PLATFORM_CPPFLAGS += $(ARCH_FLAGS) >
