From: Michal Simek <michal.si...@xilinx.com>
SGMII requires phy to be configured. The support for this has been added to
Linux and U-Boot already that's why also describe the phy via DT. Clock is
coming from si5332 chip (output 1) 125MHz which is only one GT line use on
this board.
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
Signed-off-by: Michal Simek <michal.si...@amd.com>
---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index f229880a7021..726183782305 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -42,6 +42,12 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ si5332_1: si5332_1 { /* u142 - GEM0 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
ina226-vccint {
compatible = "iio-hwmon";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint
3>;
@@ -135,8 +141,17 @@
xlnx,mio-bank = <1>;
};
+/* GEM SGMII */
+&psgtr {
+ status = "okay";
+ /* gem0 */
+ clocks = <&si5332_1>;
+ clock-names = "ref0";
+};
+
&gem0 {
status = "okay";
+ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
is-internal-pcspma;
--
2.36.0
