> The div loop uses reassign and reuse parent_rate, which causes
> the parent rate reference to be wrong after the first loop, the
> resulting clock becomes incorrect for div != 1.
> Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock")
> Signed-off-by: Loic Poulain <loic.poul...@linaro.org>
> Reviewed-by: Peng Fan <peng....@nxp.com>
Applied to u-boot-imx, master, thanks !Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =====================================================================
