From: John Schmoller <jschmol...@xes-inc.com>
According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):
"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."
The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.
Signed-off-by: John Schmoller <jschmol...@xes-inc.com>
Signed-off-by: Peter Tyser <pty...@xes-inc.com>
---
drivers/mtd/nand/fsl_upm.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index b76c673..be00555 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -21,6 +21,7 @@
static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
{
clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
+ (void)in_be32(upm->mxmr);
}
static void fsl_upm_end_pattern(struct fsl_upm *upm)
@@ -35,6 +36,7 @@ static void fsl_upm_run_pattern(struct fsl_upm *upm, int
width,
void __iomem *io_addr, u32 mar)
{
out_be32(upm->mar, mar);
+ (void)in_be32(upm->mar);
switch (width) {
case 8:
out_8(io_addr, 0x0);
--
1.7.0.4
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
