Hi Angus, could you include the UART clocks?
Am Di., 15. März 2022 um 14:09 Uhr schrieb Angus Ainslie <an...@akkea.ca>: > > This is a DM clock driver based off the imx8mm u-boot driver and the linux > kernel driver. > > All of the PLLs and clocks are initialized so the subsystems below are > functional and tested. > > 1) USB host and peripheral > 2) ECSPI > 3) UART > 4) I2C all busses > 5) USDHC for eMMC support > 6) USB storage > 7) GPIO > 8) DRAM > > Signed-off-by: Angus Ainslie <an...@akkea.ca> > --- Could you include the UART clocks? Or should I wait until your patch is accepted and then send this one after? diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index c3b685dbaa..b2d92f4776 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -82,6 +82,23 @@ static const char *imx8mq_i2c4_sels[] = {"clock-osc-25m", "sys_pll1_160m", "sys_ "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mq_uart1_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mq_uart2_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mq_uart3_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mq_uart4_sels[] = {"clock-osc-25m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + + static const char *imx8mq_wdog_sels[] = {"clock-osc-25m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -358,6 +375,16 @@ static int imx8mq_clk_probe(struct udevice *dev) imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00)); clk_dm(IMX8MQ_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80)); + + clk_dm(IMX8MQ_CLK_UART1, + imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00)); + clk_dm(IMX8MQ_CLK_UART2, + imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80)); + clk_dm(IMX8MQ_CLK_UART3, + imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000)); + clk_dm(IMX8MQ_CLK_UART4, + imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080)); + clk_dm(IMX8MQ_CLK_WDOG, imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900)); clk_dm(IMX8MQ_CLK_QSPI, @@ -387,6 +414,16 @@ static int imx8mq_clk_probe(struct udevice *dev) imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MQ_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + + clk_dm(IMX8MQ_CLK_UART1_ROOT, + imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MQ_CLK_UART2_ROOT, + imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MQ_CLK_UART3_ROOT, + imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MQ_CLK_UART4_ROOT, + imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); + clk_dm(IMX8MQ_CLK_OCOTP_ROOT, imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MQ_CLK_USDHC1_ROOT, [SNIP] -- Heiko