On 2022/3/16 23:55, Heiko Thiery wrote:
Hi Angus,
[snip]
But then something went wrong when probing uart3 ... the baudrate
switched for the uart2 (console) and the serial output became broken.
Later when the kernel starts the output becomes correct again. So the
kernel seems to configure it correctly.
see here:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpastebin.com%2Fraw%2FqXVShb3Q&data=04%7C01%7Cpeng.fan%40nxp.com%7C7f70ec10fbe643a9dc8808da07656eef%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637830429481235934%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=KYnwAT%2Bw2Vnc559Ff3QYcqjKCjpEo6mdG8lyzaeGBZo%3D&reserved=0
When I remove the "assigned-clock-parents = <&clk
IMX8MQ_SYS1_PLL_80M>;" for uart3 the output of uart2 (console) keeps
ok.
If that "fixes" it then it means that the parent IMX8MQ_SYS1_PLL_80M
clock rate is getting changed by the uart3 stanza.
Are you using the mainline devicetree file for your board ? If not could
you provide a link ?
I use the mainline u-boot/linux one.
We (thanks to Michael) found the issue. For the imx8mq the
imx_get_uartclk() returns always the values for UART1_CLK_ROOT [1].
This is wrong. Here we have to get the value dependent on the used
UART.
Yes, this needs to be fixed! Previously in U-Boot, we suppose
people not configure CCM for Uart, so all uart works at 25M OSC
if not configure CCM to other mux. Since you have CLK DM with
assigned clock parents, so this needs update.
Regards,
Peng.
[1]
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsource.denx.de%2Fu-boot%2Fu-boot%2F-%2Fblob%2Fmaster%2Farch%2Farm%2Fmach-imx%2Fimx8m%2Fclock_imx8mq.c%23L381&data=04%7C01%7Cpeng.fan%40nxp.com%7C7f70ec10fbe643a9dc8808da07656eef%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637830429481235934%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=e8CrijnqZVy2P8aVViYeiZm8jJcD6NjLqAhIriJRrt8%3D&reserved=0
