This is the only possible mux setting for the A64's PWM peripheral.

Signed-off-by: Samuel Holland <sam...@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c 
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 14d40a016b..dc52de0cf1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -571,6 +571,7 @@ static const struct sunxi_pinctrl_function 
sun50i_a64_pinctrl_functions[] = {
        { "mmc0",       2 },    /* PF0-PF5 */
        { "mmc1",       2 },    /* PG0-PG5 */
        { "mmc2",       3 },    /* PC1-PC16 */
+       { "pwm",        2 },    /* PD22 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
        { "uart0",      3 },    /* PF2-PF4 */
 #else
-- 
2.33.1

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