On Tue, 4 Jan 2022 19:35:00 -0500 Jesse Taube <mr.bossman...@gmail.com> wrote:
> From: Icenowy Zheng <icen...@aosc.io> > > This commit introduces suniv dt-bindings headers needed for > device tree files. > > Signed-off-by: Icenowy Zheng <icen...@aosc.io> > Signed-off-by: Jesse Taube <mr.bossman...@gmail.com> This seems to be some old copy, it doesn't match with what's in the Linux kernel (different name, plus clock IDs off-by-one). Please use a verbatim copy (under the same name) from the Linux kernel. Cheers, Andre > --- > include/dt-bindings/clock/suniv-ccu.h | 68 +++++++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > create mode 100644 include/dt-bindings/clock/suniv-ccu.h > > diff --git a/include/dt-bindings/clock/suniv-ccu.h > b/include/dt-bindings/clock/suniv-ccu.h > new file mode 100644 > index 0000000000..83d3c18ac0 > --- /dev/null > +++ b/include/dt-bindings/clock/suniv-ccu.h > @@ -0,0 +1,68 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ > +/* > + * Copyright (c) 2018 Icenowy Zheng <icen...@aosc.io> > + */ > + > +#ifndef _DT_BINDINGS_CLK_SUNIV_H_ > +#define _DT_BINDINGS_CLK_SUNIV_H_ > + > +#define CLK_CPU 11 > + > +#define CLK_BUS_MMC0 14 > +#define CLK_BUS_MMC1 15 > +#define CLK_BUS_DRAM 16 > +#define CLK_BUS_SPI0 17 > +#define CLK_BUS_SPI1 18 > +#define CLK_BUS_OTG 19 > +#define CLK_BUS_VE 20 > +#define CLK_BUS_LCD 21 > +#define CLK_BUS_DEINTERLACE 22 > +#define CLK_BUS_CSI 23 > +#define CLK_BUS_TVD 24 > +#define CLK_BUS_TVE 25 > +#define CLK_BUS_DE_BE 26 > +#define CLK_BUS_DE_FE 27 > +#define CLK_BUS_CODEC 28 > +#define CLK_BUS_SPDIF 29 > +#define CLK_BUS_IR 30 > +#define CLK_BUS_RSB 31 > +#define CLK_BUS_I2S0 32 > +#define CLK_BUS_I2C0 33 > +#define CLK_BUS_I2C1 34 > +#define CLK_BUS_I2C2 35 > +#define CLK_BUS_PIO 36 > +#define CLK_BUS_UART0 37 > +#define CLK_BUS_UART1 38 > +#define CLK_BUS_UART2 39 > + > +#define CLK_MMC0 40 > +#define CLK_MMC0_SAMPLE 41 > +#define CLK_MMC0_OUTPUT 42 > +#define CLK_MMC1 43 > +#define CLK_MMC1_SAMPLE 44 > +#define CLK_MMC1_OUTPUT 45 > +#define CLK_I2S 46 > +#define CLK_SPDIF 47 > + > +#define CLK_USB_PHY0 48 > + > +#define CLK_DRAM_VE 49 > +#define CLK_DRAM_CSI 50 > +#define CLK_DRAM_DEINTERLACE 51 > +#define CLK_DRAM_TVD 52 > +#define CLK_DRAM_DE_FE 53 > +#define CLK_DRAM_DE_BE 54 > + > +#define CLK_DE_BE 55 > +#define CLK_DE_FE 56 > +#define CLK_TCON 57 > +#define CLK_DEINTERLACE 58 > +#define CLK_TVE2_CLK 59 > +#define CLK_TVE1_CLK 60 > +#define CLK_TVD 61 > +#define CLK_CSI 62 > +#define CLK_VE 63 > +#define CLK_CODEC 64 > +#define CLK_AVS 65 > + > +#endif
