Scott Wood <scottw...@freescale.com> wrote on 2010/11/17 18:05:37:
>
> On Wed, 17 Nov 2010 17:57:53 +0100
> Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote:
>
> > > From: Liu Dave-R63238 <r63...@freescale.com>
> > > To: Andre Schwarz <andre.schw...@matrix-vision.de>
> > > Cc: Wood Scott-B07421 <b07...@freescale.com>, ku...@theia.denx.de, Tabi
> > > Timur-B04825 <b04...@freescale.com>, Phillips Kim-R1AAHA
> > > <r1a...@freescale.com>, Gala <ga...@kernel.crashing.org>, U-Boot List
> > > <u-boot@lists.denx.de>
> > > Date: 2010/11/15 17:58
> > > Subject: Re: [U-Boot] [PATCH] mpc83xx: Make it boot again
> > > Sent by: u-boot-boun...@lists.denx.de
> > >
> > > > The experts found an issue within init code and it looks like a proper
> > > > patch will be added to mainline shortly.
> > > > The discussion of the proper fix is right in this thread ...
> > >
> > > It should be timing issue in the SoC, software did not have a proper
> > > process to handle
> > > IMMR registers accessing.
> > >
> > > I agree Kumar on this.
> > > Adding the read back with load is needing for the LAW window changing.
> > > And something like sync/eieio instruction also need to be added between
> > > stw and lwz...
> > > to have a proper order accessing.
> >
> > After adding some more stuff in start.S I find that a lwz isn't
> > enough. An extra isync fixes this though
> >
> > lwz r4, LBLAWAR1(r3)
> > isync
> >
> > So something is missing but what? I guess isync isn't it either but
> > it works for now.
>
> As I said before, the sequence we follow in the normal I/O accessors is:
>
> lwz r4, LBLAWAR1(r3)
> twi 0, r4, 0
> isync
That works too. I do wonder if twi ..,r4,.. is correct though?
Even a
lwz r4, LBLAWAR1(r3)
nop
works.
>
> Unless we have a good reason to deviate from that -- or a good reason
> why that sequence is not necessary in general -- I think we should
> use it here as well.
Seems so. My start.S is a mess but the code added when this happened is
unrelated. It just pushes the map_xxx/remap_xxx funs further down.
Jocke
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