Sync the px30 devicetree files from Linux-5.14-rc3.

Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
 arch/arm/dts/px30-engicam-common.dtsi         |  90 +++++++++
 arch/arm/dts/px30-engicam-ctouch2.dtsi        |  22 +++
 arch/arm/dts/px30-engicam-edimm2.2.dtsi       |  59 ++++++
 .../px30-engicam-px30-core-ctouch2-of10.dts   |  77 ++++++++
 .../dts/px30-engicam-px30-core-edimm2.2.dts   |  22 +++
 arch/arm/dts/px30-evb.dts                     |  91 +++++++--
 arch/arm/dts/px30.dtsi                        | 178 +++++++++++-------
 7 files changed, 457 insertions(+), 82 deletions(-)
 create mode 100644 arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts

diff --git a/arch/arm/dts/px30-engicam-common.dtsi 
b/arch/arm/dts/px30-engicam-common.dtsi
index bd5bde989e..3429e124d9 100644
--- a/arch/arm/dts/px30-engicam-common.dtsi
+++ b/arch/arm/dts/px30-engicam-common.dtsi
@@ -6,6 +6,11 @@
  */
 
 / {
+       aliases {
+               mmc1 = &sdmmc;
+               mmc2 = &sdio;
+       };
+
        vcc5v0_sys: vcc5v0-sys {
                compatible = "regulator-fixed";
                regulator-name = "vcc5v0_sys";  /* +5V */
@@ -14,6 +19,63 @@
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
        };
+
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               clocks = <&xin32k>;
+               clock-names = "ext_clock";
+               post-power-on-delay-ms = <80>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&wifi_enable_h>;
+       };
+
+       vcc3v3_btreg: vcc3v3-btreg {
+               compatible = "regulator-gpio";
+               enable-active-high;
+               pinctrl-names = "default";
+               pinctrl-0 = <&bt_enable_h>;
+               regulator-name = "btreg-gpio-supply";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+               states = <3300000 0x0>;
+       };
+
+       vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3_rf_aux_mod";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vcc5v0_sys>;
+       };
+
+       xin32k: xin32k {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               clock-output-names = "xin32k";
+       };
+};
+
+&sdio {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       bus-width = <4>;
+       clock-frequency = <50000000>;
+       cap-sdio-irq;
+       cap-sd-highspeed;
+       keep-power-in-suspend;
+       mmc-pwrseq = <&sdio_pwrseq>;
+       non-removable;
+       sd-uhs-sdr104;
+       status = "okay";
+
+       brcmf: wifi@1 {
+               compatible = "brcm,bcm4329-fmac";
+               reg = <1>;
+       };
 };
 
 &gmac {
@@ -25,6 +87,10 @@
        status = "okay";
 };
 
+&pwm0 {
+       status = "okay";
+};
+
 &sdmmc {
        cap-sd-highspeed;
        card-detect-delay = <800>;
@@ -33,7 +99,31 @@
        status = "okay";
 };
 
+&u2phy {
+       status = "okay";
+
+       u2phy_host: host-port {
+               status = "okay";
+       };
+
+       u2phy_otg: otg-port {
+               status = "okay";
+       };
+};
+
 &uart2 {
        pinctrl-0 = <&uart2m1_xfer>;
        status = "okay";
 };
+
+&usb20_otg {
+       status = "okay";
+};
+
+&usb_host0_ehci {
+       status = "okay";
+};
+
+&usb_host0_ohci {
+       status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi 
b/arch/arm/dts/px30-engicam-ctouch2.dtsi
index 58425b1e55..bf10a3d29f 100644
--- a/arch/arm/dts/px30-engicam-ctouch2.dtsi
+++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi
@@ -6,3 +6,25 @@
  */
 
 #include "px30-engicam-common.dtsi"
+
+&pinctrl {
+       bt {
+               bt_enable_h: bt-enable-h {
+                       rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       sdio-pwrseq {
+               wifi_enable_h: wifi-enable-h {
+                       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+};
+
+&sdio_pwrseq {
+       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+       enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi 
b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
index cb00988953..449b8eb645 100644
--- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi
+++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi
@@ -5,3 +5,62 @@
  */
 
 #include "px30-engicam-common.dtsi"
+
+/ {
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               pwms = <&pwm0 0 25000 0>;
+       };
+
+       panel {
+               compatible = "yes-optoelectronics,ytc700tlag-05-201c";
+               backlight = <&backlight>;
+               data-mapping = "vesa-24";
+               power-supply = <&vcc3v3_lcd>;
+
+               port {
+                       panel_in_lvds: endpoint {
+                               remote-endpoint = <&lvds_out_panel>;
+                       };
+               };
+       };
+};
+
+&display_subsystem {
+       status = "okay";
+};
+
+&dsi_dphy {
+       status = "okay";
+};
+
+/* LVDS_B(secondary) */
+&lvds {
+       status = "okay";
+
+       ports {
+               port@1 {
+                       reg = <1>;
+
+                       lvds_out_panel: endpoint {
+                               remote-endpoint = <&panel_in_lvds>;
+                       };
+               };
+       };
+};
+
+&vopb {
+       status = "okay";
+};
+
+&vopb_mmu {
+       status = "okay";
+};
+
+&vopl {
+       status = "okay";
+};
+
+&vopl_mmu {
+       status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts 
b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
new file mode 100644
index 0000000000..47aa30505a
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+       model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
+       compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
+                    "rockchip,px30";
+
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               pwms = <&pwm0 0 25000 0>;
+       };
+
+       chosen {
+               stdout-path = "serial2:115200n8";
+       };
+
+       panel {
+               compatible = "ampire,am-1280800n3tzqw-t00h";
+               backlight = <&backlight>;
+               power-supply = <&vcc3v3_lcd>;
+               data-mapping = "vesa-24";
+
+               port {
+                       panel_in_lvds: endpoint {
+                               remote-endpoint = <&lvds_out_panel>;
+                       };
+               };
+       };
+};
+
+&display_subsystem {
+       status = "okay";
+};
+
+&dsi_dphy {
+       status = "okay";
+};
+
+&lvds {
+       status = "okay";
+
+       ports {
+               port@1 {
+                       reg = <1>;
+
+                       lvds_out_panel: endpoint {
+                               remote-endpoint = <&panel_in_lvds>;
+                       };
+               };
+       };
+};
+
+&vopb {
+       status = "okay";
+};
+
+&vopb_mmu {
+       status = "okay";
+};
+
+&vopl {
+       status = "okay";
+};
+
+&vopl_mmu {
+       status = "okay";
+};
diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts 
b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
index e54d1e480d..d759478e1c 100644
--- a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
+++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
@@ -19,3 +19,25 @@
                stdout-path = "serial2:115200n8";
        };
 };
+
+&pinctrl {
+       bt {
+               bt_enable_h: bt-enable-h {
+                       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       sdio-pwrseq {
+               wifi_enable_h: wifi-enable-h {
+                       rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+};
+
+&sdio_pwrseq {
+       reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+       enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts
index 4134e2ee13..c1ce9c295e 100644
--- a/arch/arm/dts/px30-evb.dts
+++ b/arch/arm/dts/px30-evb.dts
@@ -13,8 +13,14 @@
        model = "Rockchip PX30 EVB";
        compatible = "rockchip,px30-evb", "rockchip,px30";
 
+       aliases {
+               mmc0 = &sdmmc;
+               mmc1 = &sdio;
+               mmc2 = &emmc;
+       };
+
        chosen {
-               stdout-path = "serial2:115200n8";
+               stdout-path = "serial5:115200n8";
        };
 
        adc-keys {
@@ -126,22 +132,15 @@
        };
 
        panel@0 {
-               compatible = "sitronix,st7703";
+               compatible = "xinpeng,xpp055c272";
                reg = <0>;
                backlight = <&backlight>;
                iovcc-supply = <&vcc_1v8>;
                vci-supply = <&vcc3v3_lcd>;
 
-               ports {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       port@0 {
-                               reg = <0>;
-
-                               mipi_in_panel: endpoint {
-                                       remote-endpoint = <&mipi_out_panel>;
-                               };
+               port {
+                       mipi_in_panel: endpoint {
+                               remote-endpoint = <&mipi_out_panel>;
                        };
                };
        };
@@ -152,7 +151,6 @@
 };
 
 &emmc {
-       bus-width = <8>;
        cap-mmc-highspeed;
        mmc-hs200-1_8v;
        non-removable;
@@ -171,6 +169,11 @@
        status = "okay";
 };
 
+&gpu {
+       mali-supply = <&vdd_log>;
+       status = "okay";
+};
+
 &i2c0 {
        status = "okay";
 
@@ -388,6 +391,43 @@
        };
 };
 
+&i2c1 {
+       status = "okay";
+
+       sensor@d {
+               compatible = "asahi-kasei,ak8963";
+               reg = <0x0d>;
+               gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+               vdd-supply = <&vcc3v0_pmu>;
+               mount-matrix = "1", /* x0 */
+                              "0", /* y0 */
+                              "0", /* z0 */
+                              "0", /* x1 */
+                              "1", /* y1 */
+                              "0", /* z1 */
+                              "0", /* x2 */
+                              "0", /* y2 */
+                              "1"; /* z2 */
+       };
+
+       touchscreen@14 {
+               compatible = "goodix,gt1151";
+               reg = <0x14>;
+               interrupt-parent = <&gpio0>;
+               interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+               irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+               VDDIO-supply = <&vcc3v3_lcd>;
+       };
+
+       sensor@4c {
+               compatible = "fsl,mma7660";
+               reg = <0x4c>;
+               interrupt-parent = <&gpio0>;
+               interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
 &i2s1_2ch {
        status = "okay";
 };
@@ -464,7 +504,6 @@
 };
 
 &sdmmc {
-       bus-width = <4>;
        cap-mmc-highspeed;
        cap-sd-highspeed;
        card-detect-delay = <800>;
@@ -474,10 +513,10 @@
        sd-uhs-sdr104;
        vmmc-supply = <&vcc_sd>;
        vqmmc-supply = <&vccio_sd>;
+       status = "okay";
 };
 
 &sdio {
-       bus-width = <4>;
        cap-sd-highspeed;
        keep-power-in-suspend;
        non-removable;
@@ -486,13 +525,27 @@
        status = "okay";
 };
 
-&uart1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&uart1_xfer &uart1_cts>;
+&tsadc {
+       rockchip,hw-tshut-mode = <1>;
+       rockchip,hw-tshut-polarity = <1>;
+       status = "okay";
+};
+
+&u2phy {
        status = "okay";
+
+       u2phy_host: host-port {
+               status = "okay";
+       };
+
+       u2phy_otg: otg-port {
+               status = "okay";
+       };
 };
 
-&uart2 {
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_xfer &uart1_cts>;
        status = "okay";
 };
 
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index e892d3b5a5..248ebb61aa 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -143,7 +143,7 @@
        };
 
        arm-pmu {
-               compatible = "arm,cortex-a53-pmu";
+               compatible = "arm,cortex-a35-pmu";
                interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
@@ -244,28 +244,31 @@
                        #size-cells = <0>;
 
                        /* These power domains are grouped by VD_LOGIC */
-                       pd_usb@PX30_PD_USB {
+                       power-domain@PX30_PD_USB {
                                reg = <PX30_PD_USB>;
                                clocks = <&cru HCLK_HOST>,
                                         <&cru HCLK_OTG>,
                                         <&cru SCLK_OTG_ADP>;
                                pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+                               #power-domain-cells = <0>;
                        };
-                       pd_sdcard@PX30_PD_SDCARD {
+                       power-domain@PX30_PD_SDCARD {
                                reg = <PX30_PD_SDCARD>;
                                clocks = <&cru HCLK_SDMMC>,
                                         <&cru SCLK_SDMMC>;
                                pm_qos = <&qos_sdmmc>;
+                               #power-domain-cells = <0>;
                        };
-                       pd_gmac@PX30_PD_GMAC {
+                       power-domain@PX30_PD_GMAC {
                                reg = <PX30_PD_GMAC>;
                                clocks = <&cru ACLK_GMAC>,
                                         <&cru PCLK_GMAC>,
                                         <&cru SCLK_MAC_REF>,
                                         <&cru SCLK_GMAC_RX_TX>;
                                pm_qos = <&qos_gmac>;
+                               #power-domain-cells = <0>;
                        };
-                       pd_mmc_nand@PX30_PD_MMC_NAND {
+                       power-domain@PX30_PD_MMC_NAND {
                                reg = <PX30_PD_MMC_NAND>;
                                clocks =  <&cru HCLK_NANDC>,
                                          <&cru HCLK_EMMC>,
@@ -277,15 +280,17 @@
                                          <&cru SCLK_SFC>;
                                pm_qos = <&qos_emmc>, <&qos_nand>,
                                         <&qos_sdio>, <&qos_sfc>;
+                               #power-domain-cells = <0>;
                        };
-                       pd_vpu@PX30_PD_VPU {
+                       power-domain@PX30_PD_VPU {
                                reg = <PX30_PD_VPU>;
                                clocks = <&cru ACLK_VPU>,
                                         <&cru HCLK_VPU>,
                                         <&cru SCLK_CORE_VPU>;
                                pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+                               #power-domain-cells = <0>;
                        };
-                       pd_vo@PX30_PD_VO {
+                       power-domain@PX30_PD_VO {
                                reg = <PX30_PD_VO>;
                                clocks = <&cru ACLK_RGA>,
                                         <&cru ACLK_VOPB>,
@@ -300,8 +305,9 @@
                                         <&cru SCLK_VOPB_PWM>;
                                pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
                                         <&qos_vop_m0>, <&qos_vop_m1>;
+                               #power-domain-cells = <0>;
                        };
-                       pd_vi@PX30_PD_VI {
+                       power-domain@PX30_PD_VI {
                                reg = <PX30_PD_VI>;
                                clocks = <&cru ACLK_CIF>,
                                         <&cru ACLK_ISP>,
@@ -311,11 +317,13 @@
                                pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
                                         <&qos_isp_wr>, <&qos_isp_m1>,
                                         <&qos_vip>;
+                               #power-domain-cells = <0>;
                        };
-                       pd_gpu@PX30_PD_GPU {
+                       power-domain@PX30_PD_GPU {
                                reg = <PX30_PD_GPU>;
                                clocks = <&cru SCLK_GPU>;
                                pm_qos = <&qos_gpu>;
+                               #power-domain-cells = <0>;
                        };
                };
        };
@@ -600,7 +608,7 @@
        };
 
        wdt: watchdog@ff1e0000 {
-               compatible = "snps,dw-wdt";
+               compatible = "rockchip,px30-wdt", "snps,dw-wdt";
                reg = <0x0 0xff1e0000 0x0 0x100>;
                clocks = <&cru PCLK_WDT_NS>;
                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -703,21 +711,15 @@
                clock-names = "pclk", "timer";
        };
 
-       amba {
-               compatible = "simple-bus";
-               #address-cells = <2>;
-               #size-cells = <2>;
-               ranges;
-
-               dmac: dmac@ff240000 {
-                       compatible = "arm,pl330", "arm,primecell";
-                       reg = <0x0 0xff240000 0x0 0x4000>;
-                       interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cru ACLK_DMAC>;
-                       clock-names = "apb_pclk";
-                       #dma-cells = <1>;
-               };
+       dmac: dmac@ff240000 {
+               compatible = "arm,pl330", "arm,primecell";
+               reg = <0x0 0xff240000 0x0 0x4000>;
+               interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+               arm,pl330-periph-burst;
+               clocks = <&cru ACLK_DMAC>;
+               clock-names = "apb_pclk";
+               #dma-cells = <1>;
        };
 
        tsadc: tsadc@ff280000 {
@@ -733,9 +735,9 @@
                rockchip,grf = <&grf>;
                rockchip,hw-tshut-temp = <120000>;
                pinctrl-names = "init", "default", "sleep";
-               pinctrl-0 = <&tsadc_otp_gpio>;
+               pinctrl-0 = <&tsadc_otp_pin>;
                pinctrl-1 = <&tsadc_otp_out>;
-               pinctrl-2 = <&tsadc_otp_gpio>;
+               pinctrl-2 = <&tsadc_otp_pin>;
                #thermal-sensor-cells = <1>;
                status = "disabled";
        };
@@ -784,6 +786,16 @@
                rockchip,grf = <&grf>;
                #clock-cells = <1>;
                #reset-cells = <1>;
+
+               assigned-clocks = <&cru PLL_NPLL>,
+                       <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+                       <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+                       <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
+
+               assigned-clock-rates = <1188000000>,
+                       <200000000>, <200000000>,
+                       <150000000>, <150000000>,
+                       <100000000>, <200000000>;
        };
 
        pmucru: clock-controller@ff2bc000 {
@@ -794,6 +806,13 @@
                rockchip,grf = <&grf>;
                #clock-cells = <1>;
                #reset-cells = <1>;
+
+               assigned-clocks =
+                       <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
+                       <&pmucru SCLK_WIFI_PMU>;
+               assigned-clock-rates =
+                       <1200000000>, <100000000>,
+                       <26000000>;
        };
 
        usb2phy_grf: syscon@ff2c0000 {
@@ -803,7 +822,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
 
-               u2phy: usb2-phy@100 {
+               u2phy: usb2phy@100 {
                        compatible = "rockchip,px30-usb2phy";
                        reg = <0x100 0x20>;
                        clocks = <&pmucru SCLK_USBPHY_REF>;
@@ -856,7 +875,6 @@
                g-np-tx-fifo-size = <16>;
                g-rx-fifo-size = <280>;
                g-tx-fifo-size = <256 128 128 64 32 16>;
-               g-use-dma;
                phys = <&u2phy_otg>;
                phy-names = "usb2-phy";
                power-domains = <&power PX30_PD_USB>;
@@ -868,7 +886,6 @@
                reg = <0x0 0xff340000 0x0 0x10000>;
                interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_HOST>;
-               clock-names = "usbhost";
                phys = <&u2phy_host>;
                phy-names = "usb";
                power-domains = <&power PX30_PD_USB>;
@@ -880,7 +897,6 @@
                reg = <0x0 0xff350000 0x0 0x10000>;
                interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_HOST>;
-               clock-names = "usbhost";
                phys = <&u2phy_host>;
                phy-names = "usb";
                power-domains = <&power PX30_PD_USB>;
@@ -910,13 +926,14 @@
                status = "disabled";
        };
 
-       sdmmc: dwmmc@ff370000 {
+       sdmmc: mmc@ff370000 {
                compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff370000 0x0 0x4000>;
                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
                         <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-               clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               bus-width = <4>;
                fifo-depth = <0x100>;
                max-frequency = <150000000>;
                pinctrl-names = "default";
@@ -925,13 +942,14 @@
                status = "disabled";
        };
 
-       sdio: dwmmc@ff380000 {
+       sdio: mmc@ff380000 {
                compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff380000 0x0 0x4000>;
                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
                         <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-               clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               bus-width = <4>;
                fifo-depth = <0x100>;
                max-frequency = <150000000>;
                pinctrl-names = "default";
@@ -940,13 +958,14 @@
                status = "disabled";
        };
 
-       emmc: dwmmc@ff390000 {
+       emmc: mmc@ff390000 {
                compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff390000 0x0 0x4000>;
                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                         <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-               clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               bus-width = <8>;
                fifo-depth = <0x100>;
                max-frequency = <150000000>;
                pinctrl-names = "default";
@@ -955,6 +974,42 @@
                status = "disabled";
        };
 
+       nfc: nand-controller@ff3b0000 {
+               compatible = "rockchip,px30-nfc";
+               reg = <0x0 0xff3b0000 0x0 0x4000>;
+               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+               clock-names = "ahb", "nfc";
+               assigned-clocks = <&cru SCLK_NANDC>;
+               assigned-clock-rates = <150000000>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
+                            &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
+               power-domains = <&power PX30_PD_MMC_NAND>;
+               status = "disabled";
+       };
+
+       gpu_opp_table: opp-table2 {
+               compatible = "operating-points-v2";
+
+               opp-200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       opp-microvolt = <950000>;
+               };
+               opp-300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-microvolt = <975000>;
+               };
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-microvolt = <1050000>;
+               };
+               opp-480000000 {
+                       opp-hz = /bits/ 64 <480000000>;
+                       opp-microvolt = <1125000>;
+               };
+       };
+
        gpu: gpu@ff400000 {
                compatible = "rockchip,px30-mali", "arm,mali-bifrost";
                reg = <0x0 0xff400000 0x0 0x4000>;
@@ -965,6 +1020,7 @@
                clocks = <&cru SCLK_GPU>;
                #cooling-cells = <2>;
                power-domains = <&power PX30_PD_GPU>;
+               operating-points-v2 = <&gpu_opp_table>;
                status = "disabled";
        };
 
@@ -1017,7 +1073,6 @@
                reset-names = "axi", "ahb", "dclk";
                iommus = <&vopb_mmu>;
                power-domains = <&power PX30_PD_VO>;
-               rockchip,grf = <&grf>;
                status = "disabled";
 
                vopb_out: port {
@@ -1040,7 +1095,6 @@
                compatible = "rockchip,iommu";
                reg = <0x0 0xff460f00 0x0 0x100>;
                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-names = "vopb_mmu";
                clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
                clock-names = "aclk", "iface";
                power-domains = <&power PX30_PD_VO>;
@@ -1059,7 +1113,6 @@
                reset-names = "axi", "ahb", "dclk";
                iommus = <&vopl_mmu>;
                power-domains = <&power PX30_PD_VO>;
-               rockchip,grf = <&grf>;
                status = "disabled";
 
                vopl_out: port {
@@ -1081,8 +1134,7 @@
        vopl_mmu: iommu@ff470f00 {
                compatible = "rockchip,iommu";
                reg = <0x0 0xff470f00 0x0 0x100>;
-               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-names = "vopl_mmu";
+               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
                clock-names = "aclk", "iface";
                power-domains = <&power PX30_PD_VO>;
@@ -1091,102 +1143,102 @@
        };
 
        qos_gmac: qos@ff518000 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff518000 0x0 0x20>;
        };
 
        qos_gpu: qos@ff520000 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff520000 0x0 0x20>;
        };
 
        qos_sdmmc: qos@ff52c000 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff52c000 0x0 0x20>;
        };
 
        qos_emmc: qos@ff538000 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff538000 0x0 0x20>;
        };
 
        qos_nand: qos@ff538080 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff538080 0x0 0x20>;
        };
 
        qos_sdio: qos@ff538100 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff538100 0x0 0x20>;
        };
 
        qos_sfc: qos@ff538180 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff538180 0x0 0x20>;
        };
 
        qos_usb_host: qos@ff540000 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff540000 0x0 0x20>;
        };
 
        qos_usb_otg: qos@ff540080 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff540080 0x0 0x20>;
        };
 
        qos_isp_128: qos@ff548000 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff548000 0x0 0x20>;
        };
 
        qos_isp_rd: qos@ff548080 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff548080 0x0 0x20>;
        };
 
        qos_isp_wr: qos@ff548100 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff548100 0x0 0x20>;
        };
 
        qos_isp_m1: qos@ff548180 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff548180 0x0 0x20>;
        };
 
        qos_vip: qos@ff548200 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff548200 0x0 0x20>;
        };
 
        qos_rga_rd: qos@ff550000 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff550000 0x0 0x20>;
        };
 
        qos_rga_wr: qos@ff550080 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff550080 0x0 0x20>;
        };
 
        qos_vop_m0: qos@ff550100 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff550100 0x0 0x20>;
        };
 
        qos_vop_m1: qos@ff550180 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff550180 0x0 0x20>;
        };
 
        qos_vpu: qos@ff558000 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff558000 0x0 0x20>;
        };
 
        qos_vpu_r128: qos@ff558080 {
-               compatible = "syscon";
+               compatible = "rockchip,px30-qos", "syscon";
                reg = <0x0 0xff558080 0x0 0x20>;
        };
 
@@ -1358,7 +1410,7 @@
                };
 
                tsadc {
-                       tsadc_otp_gpio: tsadc-otp-gpio {
+                       tsadc_otp_pin: tsadc-otp-pin {
                                rockchip,pins =
                                        <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
                        };
-- 
2.25.1

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