On Tue, 2021-03-30 at 16:30 +0200, Fabien Parent wrote:
> Add MT8175 SoC support.
>
> Signed-off-by: Fabien Parent <fpar...@baylibre.com>
> ---
>
> v2:
nit: add v2 also in title
> * Removed 'usb_host' node
> * Removed some unneeded "mac" reg and interrupts definitio
> in the 'usb' node
> * Modify the u3phy and its subnode to encode the ranges property as
> <prop-encoded-array>.
>
> arch/arm/dts/mt8175.dtsi | 229 +++++++++++++++++++++++++
> arch/arm/mach-mediatek/Kconfig | 9 +
> arch/arm/mach-mediatek/Makefile | 1 +
> arch/arm/mach-mediatek/mt8175/Makefile | 3 +
> arch/arm/mach-mediatek/mt8175/init.c | 75 ++++++++
> 5 files changed, 317 insertions(+)
> create mode 100644 arch/arm/dts/mt8175.dtsi
> create mode 100644 arch/arm/mach-mediatek/mt8175/Makefile
> create mode 100644 arch/arm/mach-mediatek/mt8175/init.c
>
> diff --git a/arch/arm/dts/mt8175.dtsi b/arch/arm/dts/mt8175.dtsi
> new file mode 100644
> index 000000000000..bfb02741eef4
> --- /dev/null
> +++ b/arch/arm/dts/mt8175.dtsi
> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + * Copyright (C) 2021 BayLibre, SAS
> + * Author: Ben Ho <ben...@mediatek.com>
> + * Erin Lo <erin...@mediatek.com>
> + * Fabien Parent <fpar...@baylibre.com>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/mt8175-clk.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8175";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8175-rgu",
> + "mediatek,wdt";
> + reg = <0 0x10007000 0 0x100>;
> + #reset-cells = <1>;
> + };
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0xc000000 0 0x80000>,
> + <0 0xc080000 0 0x80000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
> +
> + sysirq: intpol-controller@10200a80 {
> + compatible = "mediatek,mt8175-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10200a80 0 0x20>;
> + };
> +
> + topckgen: topckgen@10000000 {
> + compatible = "mediatek,mt8175-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + topckgen_cg: topckgen-cg@10000000 {
> + compatible = "mediatek,mt8175-topckgen-cg", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: infracfg@10001000 {
> + compatible = "mediatek,mt8175-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8175-apmixedsys", "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + uart0: uart0@11002000 {
> + compatible = "mediatek,mt8175-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <26000000>;
> + clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg
> CLK_IFR_UART0>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart1: uart1@11003000 {
> + compatible = "mediatek,mt8175-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg
> CLK_IFR_UART1>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: uart2@11004000 {
> + compatible = "mediatek,mt8175-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11004000 0 0x1000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_CLK26M>, <&infracfg
> CLK_IFR_UART2>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
Nit: Usually sort nodes according to address
> + compatible = "mediatek,mt8175-mmc",
> "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&infracfg CLK_IFR_MSDC0_HCLK>,
> + <&infracfg CLK_IFR_MSDC0_SRC>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy: usb-phy@11cc0000 {
> + compatible = "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11cc0000 0x2000>;
> + status = "okay";
> +
> + u2port0: usb-phy@0 {
> + reg = <0 0x400>;
> + clocks = <&topckgen_cg CLK_TOP_SSUSB_PHY_CK_EN>,
> + <&topckgen_cg CLK_TOP_USB20_48M_EN>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u2port1: usb-phy@1000 {
> + reg = <0x1000 0x400>;
> + clocks = <&topckgen_cg CLK_TOP_SSUSB_PHY_CK_EN>,
> + <&topckgen_cg CLK_TOP_USB20_48M_EN>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + usb: usb@11201000 {
> + compatible ="mediatek,mt8175-mtu3", "mediatek,mtu3";
> + reg = <0 0x11203e00 0 0x0100>;
> + reg-names = "ippc";
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u2port1 PHY_TYPE_USB2>;
> + clocks = <&topckgen_cg CLK_TOP_SSUSB_TOP_CK_EN>,
> + <&infracfg CLK_IFR_SSUSB_REF>,
> + <&infracfg CLK_IFR_SSUSB_SYS>,
> + <&infracfg CLK_IFR_ICUSB>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck",
> + "dma_ck";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + ssusb: ssusb@11200000 {
> + compatible = "mediatek,ssusb";
> + reg = <0 0x11200000 0 0x3e00>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
> + status = "disabled";
> + };
> + };
> + };
> +};
For usb / phy nodes:
Reviewed-by: Chunfeng Yun <chunfeng....@mediatek.com>
Thanks a lot
> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
> index e067604d9b39..4a91fb764175 100644
> --- a/arch/arm/mach-mediatek/Kconfig
> +++ b/arch/arm/mach-mediatek/Kconfig
> @@ -41,6 +41,14 @@ config TARGET_MT7629
> including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
> switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
>
> +config TARGET_MT8175
> + bool "MediaTek MT8175 SoC"
> + select ARM64
> + help
> + The MediaTek MT8175 is a ARM64-based SoC with a quad-core Cortex-A53.
> + It is including UART, SPI, USB2.0 dual role, SD and MMC cards, NAND,
> PWM,
> + I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
> +
> config TARGET_MT8183
> bool "MediaTek MT8183 SoC"
> select ARM64
> @@ -83,6 +91,7 @@ endchoice
> source "board/mediatek/mt7622/Kconfig"
> source "board/mediatek/mt7623/Kconfig"
> source "board/mediatek/mt7629/Kconfig"
> +source "board/mediatek/mt8175/Kconfig"
> source "board/mediatek/mt8183/Kconfig"
> source "board/mediatek/mt8512/Kconfig"
> source "board/mediatek/mt8516/Kconfig"
> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
> index 0f5b0c16d2cb..ba030fb0b373 100644
> --- a/arch/arm/mach-mediatek/Makefile
> +++ b/arch/arm/mach-mediatek/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/
> obj-$(CONFIG_TARGET_MT7622) += mt7622/
> obj-$(CONFIG_TARGET_MT7623) += mt7623/
> obj-$(CONFIG_TARGET_MT7629) += mt7629/
> +obj-$(CONFIG_TARGET_MT8175) += mt8175/
> obj-$(CONFIG_TARGET_MT8183) += mt8183/
> obj-$(CONFIG_TARGET_MT8516) += mt8516/
> obj-$(CONFIG_TARGET_MT8518) += mt8518/
> diff --git a/arch/arm/mach-mediatek/mt8175/Makefile
> b/arch/arm/mach-mediatek/mt8175/Makefile
> new file mode 100644
> index 000000000000..886ab7e4eb9f
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8175/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += init.o
> diff --git a/arch/arm/mach-mediatek/mt8175/init.c
> b/arch/arm/mach-mediatek/mt8175/init.c
> new file mode 100644
> index 000000000000..5161c1ce78d5
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8175/init.c
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + * Copyright (C) 2021 BayLibre, SAS
> + * Author: Fabien Parent <fpar...@baylibre.com>
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/global_data.h>
> +#include <asm/system.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + int ret;
> +
> + ret = fdtdec_setup_memory_banksize();
> + if (ret)
> + return ret;
> +
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = gd->ram_base;
> + gd->bd->bi_dram[0].size = gd->ram_size;
> +
> + return 0;
> +}
> +
> +int mtk_pll_early_init(void)
> +{
> + return 0;
> +}
> +
> +int mtk_soc_early_init(void)
> +{
> + return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + psci_system_reset();
> +}
> +
> +int print_cpuinfo(void)
> +{
> + printf("CPU: MediaTek MT8175\n");
> + return 0;
> +}
> +
> +static struct mm_region mt8175_mem_map[] = {
> + {
> + /* DDR */
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0x40000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
> + }, {
> + .virt = 0x00000000UL,
> + .phys = 0x00000000UL,
> + .size = 0x20000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = mt8175_mem_map;
