From: motib <mo...@marvell.com>
In each pattern cycle the bus state can be changed.
In order to avoid it, we need to switch back to the same bus state on
each pattern cycle.
Signed-off-by: motib <mo...@marvell.com>
Fixed code style, removed commented code, switched to use DEBUG macros
instead of printf.
Signed-off-by: Marek Behún <marek.be...@nic.cz>
---
.../a38x/ddr3_training_centralization.c | 25 +++++++++++++++++++
.../marvell/a38x/ddr3_training_ip_engine.c | 8 ++++--
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
index 648b37ef6f..a92760681e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
@@ -24,6 +24,8 @@ u8
bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
static u8 ddr3_tip_special_rx_run_once_flag;
+extern u8 byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM];
+
static int ddr3_tip_centralization(u32 dev_num, u32 mode);
/*
@@ -110,6 +112,7 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
(max_win_size - 1) + cons_tap;
bus_start_window[mode][if_id][bus_id] = 0;
centralization_result[if_id][bus_id] = 0;
+ byte_status[if_id][bus_id] = BYTE_NOT_DEFINED;
}
}
@@ -166,6 +169,12 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
result[search_dir_id][7]));
}
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_TRACE,
+ ("byte_status[%d][%d] = 0x%x\n",
+ if_id,
+ bus_id,
+ byte_status[if_id][bus_id]));
for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
bit_id++) {
/* check if this code is valid for 2
edge, probably not :( */
@@ -174,11 +183,27 @@ static int ddr3_tip_centralization(u32 dev_num, u32 mode)
[HWS_LOW2HIGH]
[bit_id],
EDGE_1);
+ if ((byte_status[if_id][bus_id] &
BYTE_SPLIT_OUT_MIX) ||
+ (byte_status[if_id][bus_id] &
BYTE_HOMOGENEOUS_SPLIT_OUT)) {
+ if (cur_start_win[bit_id] >= 64)
+ cur_start_win[bit_id]
-= 64;
+ else
+ cur_start_win[bit_id] =
0;
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_TRACE,
+
("--------------------------\n"));
+ }
cur_end_win[bit_id] =
GET_TAP_RESULT(result
[HWS_HIGH2LOW]
[bit_id],
EDGE_1);
+ if (cur_end_win[bit_id] >= 64 &&
(byte_status[if_id][bus_id] & BYTE_SPLIT_OUT_MIX)) {
+ cur_end_win[bit_id] -= 64;
+ DEBUG_CENTRALIZATION_ENGINE
+ (DEBUG_LEVEL_TRACE,
+
("++++++++++++++++++++++++++\n"));
+ }
/* window length */
current_window[bit_id] =
cur_end_win[bit_id] -
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 5fd9a052fa..3d1fa1e74e 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -1174,7 +1174,6 @@ int ddr3_tip_ip_training_wrapper(u32 dev_num, enum
hws_access_type access_type,
/* zero the data base */
bit_bit_mask[sybphy_id] = 0;
- byte_status[if_id][sybphy_id] = BYTE_NOT_DEFINED;
for (bit_id = 0; bit_id < bit_end; bit_id++) {
h2l_adll_value[sybphy_id][bit_id] = 64;
l2h_adll_value[sybphy_id][bit_id] = 0;
@@ -1276,6 +1275,7 @@ int ddr3_tip_ip_training_wrapper(u32 dev_num, enum
hws_access_type access_type,
l2h_if_train_res = ddr3_tip_get_buf_ptr(dev_num,
HWS_LOW2HIGH, result_type, if_id);
h2l_if_train_res = ddr3_tip_get_buf_ptr(dev_num,
HWS_HIGH2LOW, result_type, if_id);
/* search from middle to end */
+
ddr3_tip_ip_training
(dev_num, ACCESS_TYPE_UNICAST,
if_id, ACCESS_TYPE_MULTICAST,
@@ -1423,7 +1423,7 @@ int ddr3_tip_ip_training_wrapper(u32 dev_num, enum
hws_access_type access_type,
* the byte can be aligned. in this case add 64
to the the low ui bits aligning it
* to the other ui bits
*/
- if (center_subphy_adll_window[sybphy_id] >= 32) {
+ if (center_subphy_adll_window[sybphy_id] >= 32 ||
bit_bit_mask[sybphy_id] != 0x0) {
byte_status[if_id][sybphy_id] =
BYTE_SPLIT_OUT_MIX;
DEBUG_TRAINING_IP_ENGINE
@@ -1432,8 +1432,12 @@ int ddr3_tip_ip_training_wrapper(u32 dev_num, enum
hws_access_type access_type,
if_id, sybphy_id,
byte_status[if_id][sybphy_id]));
for (bit_id = 0; bit_id < bit_end; bit_id++) {
if (bit_state[sybphy_id *
BUS_WIDTH_IN_BITS + bit_id] == BIT_LOW_UI) {
+ if (bit_bit_mask[sybphy_id] &
(1 << bit_id))
+ continue;
l2h_if_train_res[sybphy_id *
BUS_WIDTH_IN_BITS + bit_id] += 64;
+
l2h_adll_value[sybphy_id][bit_id] = l2h_if_train_res[sybphy_id *
BUS_WIDTH_IN_BITS + bit_id];
h2l_if_train_res[sybphy_id *
BUS_WIDTH_IN_BITS + bit_id] += 64;
+
h2l_adll_value[sybphy_id][bit_id] = h2l_if_train_res[sybphy_id *
BUS_WIDTH_IN_BITS + bit_id];
}
DEBUG_TRAINING_IP_ENGINE
(DEBUG_LEVEL_TRACE,
--
2.26.2
