On 1/21/21 9:40 PM, Aswath Govindraju wrote: > From: Faiz Abbas <[email protected]> > > Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB > flag to indicate the same. > > Also move the write of trm_icp and driver strength to the set_clock() > function to match the kernel configuration flow. > > Signed-off-by: Faiz Abbas <[email protected]> > Signed-off-by: Aswath Govindraju <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]> Best Regards, Jaehoon Chung > --- > drivers/mmc/am654_sdhci.c | 26 ++++++++++++++------------ > 1 file changed, 14 insertions(+), 12 deletions(-) > > diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c > index e0136dff9711..1e0654183811 100644 > --- a/drivers/mmc/am654_sdhci.c > +++ b/drivers/mmc/am654_sdhci.c > @@ -84,6 +84,7 @@ struct am654_sdhci_plat { > #define IOMUX_PRESENT BIT(1) > #define FREQSEL_2_BIT BIT(2) > #define STRBSEL_4_BIT BIT(3) > +#define DLL_CALIB BIT(4) > }; > > struct timing_data { > @@ -195,6 +196,15 @@ static int am654_sdhci_set_ios_post(struct sdhci_host > *host) > freqsel << FREQSEL_SHIFT); > } > > + /* Configure DLL TRIM */ > + mask = DLL_TRIM_ICP_MASK; > + val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; > + > + /* Configure DLL driver strength */ > + mask |= DR_TY_MASK; > + val |= plat->drv_strength << DR_TY_SHIFT; > + regmap_update_bits(plat->base, PHY_CTRL1, mask, val); > + > /* Enable DLL */ > regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, > 0x1 << ENDLL_SHIFT); > @@ -221,7 +231,7 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat) > mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; > regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0); > > - if (plat->flags & DLL_PRESENT) { > + if (plat->flags & DLL_CALIB) { > regmap_read(plat->base, PHY_STAT1, &val); > if (~val & CALDONE_MASK) { > /* Calibrate IO lines */ > @@ -233,15 +243,6 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat) > if (ret) > return ret; > } > - > - /* Configure DLL TRIM */ > - mask = DLL_TRIM_ICP_MASK; > - val = plat->trm_icp << DLL_TRIM_ICP_SHIFT; > - > - /* Configure DLL driver strength */ > - mask |= DR_TY_MASK; > - val |= plat->drv_strength << DR_TY_SHIFT; > - regmap_update_bits(plat->base, PHY_CTRL1, mask, val); > } > > /* Enable pins by setting IO mux to 0 */ > @@ -292,12 +293,13 @@ const struct sdhci_ops am654_sdhci_ops = { > > const struct am654_driver_data am654_drv_data = { > .ops = &am654_sdhci_ops, > - .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT, > + .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB | > + STRBSEL_4_BIT, > }; > > const struct am654_driver_data j721e_8bit_drv_data = { > .ops = &am654_sdhci_ops, > - .flags = DLL_PRESENT, > + .flags = DLL_PRESENT | DLL_CALIB, > }; > > static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host) >
