On Thu, Jan 07, 2021 at 11:12:16AM +0100, Marek Vasut wrote: > The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words > after the descriptor. Use this to pad the descriptors to cacheline size and > remove the need for noncached memory altogether. Moreover, this lets Tegra > use the generic cache flush / invalidate operations. > > Signed-off-by: Marek Vasut <ma...@denx.de> > Cc: Joe Hershberger <joe.hershber...@ni.com> > Cc: Patrice Chotard <patrice.chot...@st.com> > Cc: Patrick Delaunay <patrick.delau...@st.com> > Cc: Ramon Fried <rfried....@gmail.com> > Cc: Stephen Warren <swar...@nvidia.com> > Tested-by: Stephen Warren <swar...@nvidia.com> > Reviewed-by: Stephen Warren <swar...@nvidia.com> > Tested-by: Patrice Chotard <patrice.chot...@foss.st.com>
Applied to u-boot/master, thanks! -- Tom
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