On 1/7/21 3:12 AM, Marek Vasut wrote: > The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words > after the descriptor. Use this to pad the descriptors to cacheline size and > remove the need for noncached memory altogether. Moreover, this lets Tegra > use the generic cache flush / invalidate operations.
Tested-by: Stephen Warren <swar...@nvidia.com> Reviewed-by: Stephen Warren <swar...@nvidia.com>
