> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin....@intel.com>
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Tan, Ley Foon
> <ley.foon....@intel.com>; See, Chin Liang <chin.liang....@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> <tien.fong.c...@intel.com>; Westergreen, Dalon
> <dalon.westergr...@intel.com>; Simon Glass <s...@chromium.org>; Gan,
> Yau Wai <yau.wai....@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin....@intel.com>
> Subject: [RESEND v2 13/22] arm: socfpga: Move Stratix10 and Agilex clock
> manager common code
>
> Move duplicated function cm_get_qspi_controller_clk_hz to
> clock_manager.c.
>
> Signed-off-by: Siew Chin Lim <elly.siew.chin....@intel.com>
> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> ---
> arch/arm/mach-socfpga/clock_manager.c | 10 ++++++++++
> arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------
> arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------
> arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++
> arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
> 5 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-
> socfpga/clock_manager.c
> index a4a97b6a0f..2d0cc19f7a 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -9,6 +9,7 @@
> #include <wait_bit.h>
> #include <asm/io.h>
> #include <asm/arch/clock_manager.h>
> +#include <asm/arch/system_manager.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -62,6 +63,15 @@ int set_cpu_clk_info(void)
> return 0;
> }
>
> +#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
> +unsigned int cm_get_qspi_controller_clk_hz(void)
> +{
> + return readl(socfpga_get_sysmgr_addr() +
> + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); }
> +
> +#endif
> +
> #ifndef CONFIG_SPL_BUILD
> static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
> char *const argv[])
> diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
> b/arch/arm/mach-socfpga/clock_manager_agilex.c
> index 6188a8c3d2..86e00d7611 100644
> --- a/arch/arm/mach-socfpga/clock_manager_agilex.c
> +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
> @@ -64,12 +64,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
> return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
> }
>
> -u32 cm_get_qspi_controller_clk_hz(void)
> -{
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> -}
> -
> void cm_print_clock_quick_summary(void)
> {
> printf("MPU %10d kHz\n",
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c
> b/arch/arm/mach-socfpga/clock_manager_s10.c
> index 431794e082..ef62c56ad9 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -383,12 +383,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> return clock;
> }
>
> -unsigned int cm_get_qspi_controller_clk_hz(void)
> -{
> - return readl(socfpga_get_sysmgr_addr() +
> - SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
> -}
> -
> unsigned int cm_get_spi_controller_clk_hz(void)
> {
> u32 clock = cm_get_l3_main_clk_hz();
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 1f734bcd65..0f0cb230fa 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void
> cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void
> cm_print_clock_quick_summary(void);
> +
> +#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
> +unsigned int cm_get_qspi_controller_clk_hz(void);
> +#endif
> #endif
Cyclone 5 and Arria 10 also have this function.
This is also define in include/configs/*.h. Check where should add it.
Regards
Ley Foon
