> -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin....@intel.com> > Sent: Tuesday, November 10, 2020 2:44 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut <ma...@denx.de>; Tan, Ley Foon > <ley.foon....@intel.com>; See, Chin Liang <chin.liang....@intel.com>; > Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong > <tien.fong.c...@intel.com>; Westergreen, Dalon > <dalon.westergr...@intel.com>; Simon Glass <s...@chromium.org>; Gan, > Yau Wai <yau.wai....@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin....@intel.com> > Subject: [RESEND v2 07/22] arm: socfpga: Rearrange sequence of macros in > handoff_soc64.h > > No functionality change. In preparation for Stratix10 and Agilex handoff > function restructuring. > This patch adding new macros, please add description for this in commit message. Regards Ley Foon
- [RESEND v2 02/22] arm: socfpga: dm: Add base address for Int... Siew Chin Lim
- [RESEND v2 04/22] arm: socfpga: Rename Stratix10 and Agilex ... Siew Chin Lim
- [RESEND v2 03/22] arm: socfpga: dm: Add firewall support for... Siew Chin Lim
- [RESEND v2 11/22] arm: socfpga: dm: Get clock manager base a... Siew Chin Lim
- [RESEND v2 08/22] arm: socfpga: Restructure Stratix10 and Ag... Siew Chin Lim
- [RESEND v2 07/22] arm: socfpga: Rearrange sequence of macros... Siew Chin Lim
- RE: [RESEND v2 07/22] arm: socfpga: Rearrange sequence ... Tan, Ley Foon
- [RESEND v2 10/22] drivers: clk: dm: Add clock driver for Dia... Siew Chin Lim
- [RESEND v2 09/22] arm: socfpga: Add handoff data support for... Siew Chin Lim
- [RESEND v2 14/22] arm: socfpga: Changed to store QSPI refere... Siew Chin Lim
- [RESEND v2 12/22] drivers: clk: dm: Add memory clock driver ... Siew Chin Lim
- [RESEND v2 13/22] arm: socfpga: Move Stratix10 and Agilex cl... Siew Chin Lim