On Mon, Sep 14, 2020 at 10:23 PM Sean Anderson <sean...@gmail.com> wrote: > > Clearing MIP.MSIP is not guaranteed to do anything by the spec. In > addition, most existing RISC-V hardware does nothing when this bit is set. > > The following commits "riscv: Use a valid bit to ignore already-pending > IPIs" and "riscv: Clear pending IPIs on initialization" should implement > the original intent of the reverted commit in a more robust manner. > > This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6. > > Signed-off-by: Sean Anderson <sean...@gmail.com> > --- > I know there is still some discussion in the last series on whether to include > this commit, but I'd like to put out another revision and get feedback. > > (no changes since v1) > > arch/riscv/cpu/start.S | 2 -- > 1 file changed, 2 deletions(-) >
Reviewed-by: Bin Meng <bin.m...@windriver.com>
