On Tue, Sep 8, 2020 at 2:17 AM Sean Anderson <sean...@gmail.com> wrote: > > Some IPIs may already be pending when U-Boot is started. This could be a > problem if a secondary hart tries to handle an IPI before the boot hart has > initialized the IPI device. > > This commit uses NULL as a sentinel for secondary harts so they know when > the IPI is initialized, and it is safe to use the IPI API. The smp addr > parameter is initialized to NULL by board_init_f_init_reserve. Before this, > secondary harts wait in wait_for_gd_init. > > This imposes a minor restriction because harts may no longer jump to NULL. > However, given that the RISC-V debug device is likely to be located at > 0x400, it is unlikely for any RISC-V implementation to have usable ram > located at 0x0. > > Signed-off-by: Sean Anderson <sean...@gmail.com> > --- > > arch/riscv/lib/smp.c | 26 ++++++++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) >
Reviewed-by: Bin Meng <bin.m...@windriver.com>
