Am 9. August 2020 18:35:45 MESZ schrieb Sean Anderson <sean...@gmail.com>:
>On 8/9/20 12:14 PM, Heinrich Schuchardt wrote:
>> Hello Sean,
>>
>> while trying to understand the handling of SMP I stumbled of this
>question:
>>
>> Why did you define CONFIG_SYS_INIT_SP_ADDR as an odd number on the
>MAIX
>> in commit a7c81fc85326 ("riscv: Add Sipeed Maix support") while the
>> other RISC-V boards use an even number:
>>
>> include/configs/sifive-fu540.h:29:
>> 29 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE +
>SZ_2M)
>>
>> include/configs/qemu-riscv.h:22:
>> 22 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE +
>SZ_2M)
>>
>> include/configs/sipeed-maix.h:13:
>> 13 | #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
>>
>> I always thought that RISC-V stack pointers must be 16 byte aligned:
>>
>> Cf. https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf
>>
>> "In the standard RISC-V calling convention, the stack grows downward
>and
>> the stack pointer is always kept 16-byte aligned."
>
>Because that is the top of (non-ai) ram. And it gets 16-byte aligned by
>call_board_init_f anyway.
>
>--Sean
Top of RAM is the place to which we want to relocate U-Boot. But furthermore
this value minus a multiple of16KiB is also used for the stack lication of the
secondary CPU.
Shouldn't we better use the same definition as the other boards?
