Hello Sean,
while trying to understand the handling of SMP I stumbled of this question:
Why did you define CONFIG_SYS_INIT_SP_ADDR as an odd number on the MAIX
in commit a7c81fc85326 ("riscv: Add Sipeed Maix support") while the
other RISC-V boards use an even number:
include/configs/sifive-fu540.h:29:
29 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
include/configs/qemu-riscv.h:22:
22 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
include/configs/sipeed-maix.h:13:
13 | #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
I always thought that RISC-V stack pointers must be 16 byte aligned:
Cf. https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf
"In the standard RISC-V calling convention, the stack grows downward and
the stack pointer is always kept 16-byte aligned."
Best regards
Heinrich
