> -----Original Message-----
> From: Ang, Chee Hong <chee.hong....@intel.com>
> Sent: Wednesday, August 5, 2020 6:35 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschm...@gmail.com>; Tom Rini <tr...@konsulko.com>; See,
> Chin Liang <chin.liang....@intel.com>; Tan, Ley Foon
> <ley.foon....@intel.com>; Ang, Chee Hong <chee.hong....@intel.com>;
> Chee, Tien Fong <tien.fong.c...@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin....@intel.com>
> Subject: [PATCH v1] configs: socfpga: soc64: Avoid SPL enter infinite loop
> during exception
>
> From: Chin Liang See <chin.liang....@intel.com>
>
> In current implementation, any exception would trigger a CPU reset.
> But a bad written SPL would cause infinite loop where the system will reload
> the same SPL instead of loading factory safe image.
>
> Hence this patch is to ensure any exception will cause a hang. At this
> moment, watchdog shall be triggered and Remote System Update
> mechanism shall load the next production image or factory safe image.
>
> Signed-off-by: Chin Liang See <chin.liang....@intel.com>
> Signed-off-by: Chee Hong Ang <chee.hong....@intel.com>
> ---
> configs/socfpga_agilex_defconfig | 1 +
> configs/socfpga_stratix10_defconfig | 1 +
> 2 files changed, 2 insertions(+)
>
Reviewed-by: Ley Foon Tan <ley.foon....@intel.com>
Regards
Ley Foon
