Hello. tma...@apm.com wrote:
> From: Tirumala Marri <tma...@apm.com> > This patch adds L2Cache/SRAM and OCM register definitions. > Signed-off-by: Tirumala R Marri <tma...@apm.com> [...] > diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h > b/arch/powerpc/include/asm/ppc4xx-isram.h > index d6d17ac..b723401 100644 > --- a/arch/powerpc/include/asm/ppc4xx-isram.h > +++ b/arch/powerpc/include/asm/ppc4xx-isram.h > @@ -25,7 +25,8 @@ > /* > * Internal SRAM > */ > -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) > +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||\ Please add space before \ to keep the style consistent. > + defined(CONFIG_APM82XXX) > #define ISRAM0_DCR_BASE 0x380 > #else > #define ISRAM0_DCR_BASE 0x020 > @@ -42,7 +43,8 @@ > #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ > #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ > > -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) > +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) ||\ Same here... > + defined(CONFIG_APM82XXX) > #define ISRAM1_DCR_BASE 0x0B0 > #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ > #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ WBR, Sergei _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot