From: Tirumala Marri <tma...@apm.com>

This patch adds L2Cache/SRAM and OCM register definitions.

Signed-off-by: Tirumala R Marri <tma...@apm.com>
---
 arch/powerpc/include/asm/ppc4xx-isram.h |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h 
b/arch/powerpc/include/asm/ppc4xx-isram.h
index d6d17ac..b723401 100644
--- a/arch/powerpc/include/asm/ppc4xx-isram.h
+++ b/arch/powerpc/include/asm/ppc4xx-isram.h
@@ -25,7 +25,8 @@
 /*
  * Internal SRAM
  */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||\
+    defined(CONFIG_APM82XXX)
 #define ISRAM0_DCR_BASE 0x380
 #else
 #define ISRAM0_DCR_BASE 0x020
@@ -42,7 +43,8 @@
 #define ISRAM0_REVID   (ISRAM0_DCR_BASE+0x09)  /* SRAM bus revision id reg */
 #define ISRAM0_DPC     (ISRAM0_DCR_BASE+0x0a)  /* SRAM data parity check reg */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) ||\
+    defined(CONFIG_APM82XXX)
 #define ISRAM1_DCR_BASE 0x0B0
 #define ISRAM1_SB0CR   (ISRAM1_DCR_BASE+0x00)  /* SRAM1 bank config 0*/
 #define ISRAM1_BEAR    (ISRAM1_DCR_BASE+0x04)  /* SRAM1 bus error addr reg */
@@ -60,7 +62,7 @@
 #if defined (CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM82XXX)
 #define L2_CACHE_BASE  0x030
 #define L2_CACHE_CFG   (L2_CACHE_BASE+0x00)    /* L2 Cache Config      */
 #define L2_CACHE_CMD   (L2_CACHE_BASE+0x01)    /* L2 Cache Command     */
-- 
1.6.1.rc3

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