> -----Original Message-----
> From: Ioana Ciornei <ioana.cior...@nxp.com>
> Sent: Monday, April 27, 2020 3:21 PM
> To: Priyanka Jain <priyanka.j...@nxp.com>; u-boot@lists.denx.de
> Cc: Alexandru Marginean <alexandru.margin...@nxp.com>; Madalin Bucur
> <madalin.bu...@nxp.com>; Florin Laurentiu Chiculita
> <florinlaurentiu.chicul...@nxp.com>; Razvan Ionut Cirjan
> <razvanionut.cir...@nxp.com>; Ioana Ciornei <ioana.cior...@nxp.com>
> Subject: [PATCH v2 2/6] arm: dts: lx2160aqds: add MDIO slots
>
> The LX2160A processor has two external MDIO interfaces, described in the
> DTS as emdio1 and emdio2.
>
> On the LX2160AQDS board EMDIO1 is used with two onboard RGMII PHYs
> (Realtek RTL8211FD-CG), as well as eight input/output connectors for
> mezzanine cards. Configuration signals from the Qixis FPGA control the
> routing of the external MDIOs.
>
> Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of
> the 8 IO slots. As a consequence, a new node is added to describe register
> 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as
> MDIO buses.
>
> Also, DPMAC 17 and 18 are updated to reference the on-board PHYs.
>
> Signed-off-by: Ioana Ciornei <ioana.cior...@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cir...@nxp.com>
Thanks,
Razvan
> ---
> Changes in v2:
> - reword commit message
>
>
> arch/arm/dts/fsl-lx2160a-qds.dts | 115 ++++++++++++++++++++++++++++++-
> 1 file changed, 114 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-
> qds.dts
> index 592fd5977e27..4946ce8dfba8 100644
> --- a/arch/arm/dts/fsl-lx2160a-qds.dts
> +++ b/arch/arm/dts/fsl-lx2160a-qds.dts
> @@ -2,7 +2,7 @@
> /*
> * NXP LX2160AQDS device tree source
> *
> - * Copyright 2018-2019 NXP
> + * Copyright 2018-2020 NXP
> *
> */
>
> @@ -18,6 +18,26 @@
> };
> };
>
> +&dpmac17 {
> + status = "okay";
> + phy-handle = <&rgmii_phy1>;
> + phy-connection-type = "rgmii-id";
> +};
> +
> +&dpmac18 {
> + status = "okay";
> + phy-handle = <&rgmii_phy2>;
> + phy-connection-type = "rgmii-id";
> +};
> +
> +&emdio1 {
> + status = "okay";
> +};
> +
> +&emdio2 {
> + status = "okay";
> +};
> +
> &esdhc0 {
> status = "okay";
> };
> @@ -30,6 +50,99 @@
> status = "okay";
> u-boot,dm-pre-reloc;
>
> + fpga@66 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "simple-mfd";
> + reg = <0x66>;
> +
> + mux-mdio@54 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "mdio-mux-i2creg";
> + reg = <0x54>;
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
> + mdio-parent-bus = <&emdio1>;
> +
> + mdio@00 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x00>;
> +
> + rgmii_phy1: ethernet-phy@1 {
> + reg = <0x1>;
> + };
> + };
> + mdio@08 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x40>;
> +
> + rgmii_phy2: ethernet-phy@2 {
> + reg = <0x2>;
> + };
> + };
> +
> + emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
> + reg = <0xC0>;
> + device-name = "emdio1_slot1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
> + reg = <0xC8>;
> + device-name = "emdio1_slot2";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
> + reg = <0xD0>;
> + device-name = "emdio1_slot3";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
> + reg = <0xD8>;
> + device-name = "emdio1_slot4";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
> + reg = <0xE0>;
> + device-name = "emdio1_slot5";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
> + reg = <0xE8>;
> + device-name = "emdio1_slot6";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
> + reg = <0xF0>;
> + device-name = "emdio1_slot7";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
> + reg = <0xF8>;
> + device-name = "emdio1_slot8";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + };
> +
> i2c-mux@77 {
> compatible = "nxp,pca9547";
> reg = <0x77>;
> --
> 2.17.1
