Dear Marek, > From: Marek Vasut <ma...@denx.de> > Sent: lundi 23 mars 2020 02:45 > > The RX descriptor field 3 should contain only OWN and BUF1V bits before being > used for receiving data by the DMA engine. However, right now, if the > descriptor > was already used for receiving data and is being cleared, the field 3 is only > modified and the aforementioned two bits are ORRed into the field. This could > lead > to a residual dirty bits being left in the field 3 from previous transfer, > and it > generally does. Fully set the field 3 instead to clear those residual dirty > bits. > > Signed-off-by: Marek Vasut <ma...@denx.de> > Cc: Joe Hershberger <joe.hershber...@ni.com> > Cc: Patrice Chotard <patrice.chot...@st.com> > Cc: Patrick Delaunay <patrick.delau...@st.com> > Cc: Ramon Fried <rfried....@gmail.com> > Cc: Stephen Warren <swar...@nvidia.com> > --- > drivers/net/dwc_eth_qos.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index > 0564bebf76..4bce6d4290 100644 > --- a/drivers/net/dwc_eth_qos.c
Reviewed-by: Patrick Delaunay <patrick.delau...@st.com> Thanks Patrick
