On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
supports it. But Linux as of now expects to get the flash in 1S-1S-1S
mode. Handing the flash to Linux in Octal DTR mode means the kernel will
fail to detect the flash.
So, we need to reset to Power-on-Reset (POR) state before handing off
the flash. A Software Reset command can be used to do this. Since the
command is optional, flashes have to specify they support it by using
the flag 'SPI_NOR_SOFT_RESET'.
One limitation of the soft reset is that it will restore state from
non-volatile registers in some flashes. This means that if the flash was
set to 8D mode in a non-volatile configuration, a soft reset won't help.
This commit assumes that we don't set any non-volatile bits anywhere,
and the flash doesn't have any non-volatile Octal DTR mode
configuration.
Signed-off-by: Pratyush Yadav <p.ya...@ti.com>
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/sf_probe.c | 9 +++++
drivers/mtd/spi/spi-nor-core.c | 66 ++++++++++++++++++++++++++++++++++
include/linux/mtd/spi-nor.h | 11 ++++++
4 files changed, 87 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 5780c81287..37e6657490 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -68,6 +68,7 @@ struct flash_info {
#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
#define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */
+#define SPI_NOR_SOFT_RESET BIT(18) /* Flash supports soft reset command */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 72b6ee702d..90bd3196c2 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -152,6 +152,14 @@ int spi_flash_std_probe(struct udevice *dev)
static int spi_flash_std_remove(struct udevice *dev)
{
+ struct spi_flash *flash;
+ int ret;
+
+ flash = dev_get_uclass_priv(dev);
+ ret = spi_nor_remove(flash);
+ if (ret)
+ return ret;
+
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
spi_flash_mtd_unregister();
#endif
@@ -178,6 +186,7 @@ U_BOOT_DRIVER(spi_flash_std) = {
.remove = spi_flash_std_remove,
.priv_auto_alloc_size = sizeof(struct spi_flash),
.ops = &spi_flash_std_ops,
+ .flags = DM_FLAG_OS_PREPARE,
};
#endif /* CONFIG_DM_SPI_FLASH */
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index f05217fe7b..839d8a18df 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -186,6 +186,8 @@ struct spi_nor_fixups {
struct spi_nor_flash_parameter *params);
};
+#define SPI_NOR_SRST_SLEEP_LEN 200
+
/**
* spi_nor_get_cmd_ext() - Get the command opcode extension based on the
* extension type.
@@ -2812,6 +2814,67 @@ static int spi_nor_init(struct spi_nor *nor)
return 0;
}
+/**
+ * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence
+ * @nor: the spi_nor structure
+ *
+ * This function can be used to switch from Octal DTR mode to legacy mode on a
+ * flash that supports it. The soft reset is executed in Octal DTR mode.
+ *
+ * Return: 0 for success, -errno for failure.
+ */
+static int spi_nor_soft_reset(struct spi_nor *nor)
+{
+ struct spi_mem_op op;
+ int ret;
+ enum spi_nor_cmd_ext ext;
+
+ ext = nor->cmd_ext_type;
+ nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+
+ op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 8),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DATA);
+ spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
+ ret = spi_mem_exec_op(nor->spi, &op);
+ if (ret) {
+ dev_warn(nor->dev, "Software reset enable failed: %d\n", ret);
+ goto out;
+ }
+
+ op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 8),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DATA);
+ spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
+ ret = spi_mem_exec_op(nor->spi, &op);
+ if (ret) {
+ dev_warn(nor->dev, "Software reset failed: %d\n", ret);
+ goto out;
+ }
+
+ /*
+ * Software Reset is not instant, and the delay varies from flash to
+ * flash. Looking at a few flashes, most range somewhere below 100
+ * microseconds. So, wait for 200ms just to be sure.
+ */
+ udelay(SPI_NOR_SRST_SLEEP_LEN);
+
+out:
+ nor->cmd_ext_type = ext;
+ return ret;
+}
+
+int spi_nor_remove(struct spi_nor *nor)
+{
+ if (nor->info->flags & SPI_NOR_OCTAL_DTR_READ &&
+ nor->flags & SNOR_F_SOFT_RESET)
+ return spi_nor_soft_reset(nor);
+
+ return 0;
+}
+
int spi_nor_scan(struct spi_nor *nor)
{
struct spi_nor_flash_parameter params;
@@ -2894,6 +2957,9 @@ int spi_nor_scan(struct spi_nor *nor)
if (info->flags & USE_CLSR)
nor->flags |= SNOR_F_USE_CLSR;
+ if (info->flags & SPI_NOR_SOFT_RESET)
+ nor->flags |= SNOR_F_SOFT_RESET;
+
if (info->flags & SPI_NOR_NO_ERASE)
mtd->flags |= MTD_NO_ERASE;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index defd0d2d3d..58992f02b4 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -66,6 +66,8 @@
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address
Register */
#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address
Register */
+#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
+#define SPINOR_OP_SRST 0x99 /* Software Reset */
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
@@ -247,6 +249,7 @@ enum spi_nor_option_flags {
SNOR_F_READY_XSR_RDY = BIT(4),
SNOR_F_USE_CLSR = BIT(5),
SNOR_F_BROKEN_RESET = BIT(6),
+ SNOR_F_SOFT_RESET = BIT(7),
};
struct spi_nor;
@@ -550,4 +553,12 @@ device_node *spi_nor_get_flash_node(struct spi_nor *nor)
*/
int spi_nor_scan(struct spi_nor *nor);
+/**
+ * spi_nor_remove() - perform cleanup before booting to the next stage
+ * @nor: the spi_nor structure
+ *
+ * Return: 0 for success, -errno for failure.
+ */
+int spi_nor_remove(struct spi_nor *nor);
+
#endif
--
2.25.0
